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Service Telephone:86-755-83294757
Trade Name:AD7366BRUZ
Data Manual:AD7366BRUZ.pdf
Brand:ADI
Particular Year:23+
Package:TSSOP24
Delivery Date:New and Original
Stock: 1030pcs
The AD7366BRUZ is a dual-core 12-bit/14-bit, high-speed, low-power, successive-approximation analogue-to-digital converter (ADC) with up to 1 MSPS of throughput. two ADCs are built into the device, both of which are preceded by a dual-channel multiplexer and a low-noise, wide-bandwidth sample-and-hold amplifier.
The AD7366BRUZ is manufactured using ADI's industrial CMOS process (iCMOS1), a technology platform that combines the benefits of both low-voltage and high-voltage CMOS. Using the iCMOS process, the AD7366 not only reduces power consumption and package size, but also accepts high-voltage bipolar signals.The AD7366 can input ±10 V range, ±5 V range and 0 V to 10 V range of true bipolar analogue signals.
The AD7367 has a 2.5 V on-chip reference voltage source, which can be disabled to use an external reference voltage source. The AD7366BRUZ can accept ±12 V true bipolar analogue inputs if a 3 V reference voltage is applied to the DCAPA and DCAPB pins. For the ±12 V input range, a minimum ±12 V VDD and VSS supply is required.
Device Features
Dual-core 12-bit/14-bit, dual-channel ADCs
True bipolar analogue inputs
Programmable Input Parameters
±10 V, ±5 V, 0 V to 10 V
±12 V (with 3 V external reference)
Throughput rate: 1 MSPS
Simultaneous conversion and readout in less than 1 μs
Low power consumption:
8.3 mA in normal mode (typical)
320 nA in shutdown mode (typical)
High analogue input impedance
AD7366
Signal-to-noise ratio: 72 dB (50 kHz input frequency)
12-bit lossless code
AD7367
Signal-to-noise ratio: 76 dB (50 kHz input frequency)
14-bit lossless code
Accurate 2.5 V ± 0.2% on-chip reference voltage source
Operating temperature range: -40°C to +85°C
High-speed serial interface, SPI®, QSPI™, MICROWIRE™ and DSP compatible
Model
Brand
Package
Quantity
Describe
TI
VSSOP-10
15000
16-bit analogue-to-digital converter, 2, 4 inputs, 1 triangular integration, 10-VSSOP
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