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The 8V19N491-24NLGI is a fully integrated FemtoClock NG jitter attenuator and clock frequency synthesizer, designed as a high-performance clock solution for conditioning and frequency/phase management of radio equipment boards in wireless base stations. This device has been optimized to provide the outstanding phase noise performance required for the implementation of GSM, WCDMA, LTE, LTE-A and 5G radio boards.

The 8V19N491-24NLGI supports JESD204B/C subclass 0 and 1 clocks. The two-level PLL architecture supports jitter attenuation and frequency doubling. The first-level PLL is a jitter attenuator, which uses an external VCXO to achieve the best phase noise characteristics. The second-level PLL locks the VCXO-PLL output signal and synthesizes the target frequency.

The 8V19N491-24NLGI mainly has the following features:

High-performance clock RF-PLL supporting JESD204B/C

Optimized for low phase noise :-153 DBC /Hz (1MHz offset), 245.76MHz clock

The typical value of integral phase noise is 61fs RMS(12 khz - 20 MHz).

Dual PLL architecture

The first PLL-level built-in external VCXO is used for clock jitter attenuation

The second PLL is equipped with a built-in femtosecond NG PLL: 2457.6MHz

For 3932.16MHz: 8V19N492-39

For 1966.08MHz: 8V19N490-19

For 2949.12MHz: 8V19N492 and 8V19N490A

For 3686.4MHz: 8V19N491-36

Five output channels, totaling 15 outputs

Configurable integer clock divider

The low-power LVPECL/LVDS output supports configurable signal amplitudes, DC and AC coupling, as well as LVPECL and LVDS line termination technologies

Phase delay circuit

Dual-input redundant input clock architecture

The generation modes of SYSREF include the internal and external trigger modes of JESD204B/C

Power supply voltage :3.3V

SPI interface, 3/4 wire configurable

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