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The 8V19N490BBDGI is a fully integrated FemtoClock® NG jitter attenuator and clock frequency synthesizer, designed as a high-performance clock solution for conditioning and frequency/phase management of radio equipment boards in wireless base stations.

This jitter attenuator mainly includes the following features:

High-performance clock RF-PLL supporting JESD204B

Optimized for low phase noise :-150 DBC /Hz (800kHz offset; 245.76MHz clock

The typical value of integral phase noise is 52fs RMS(12 khz to 20MHz).

Dual PLL architecture

The first PLL-level built-in external VCXO is used for clock jitter attenuation

The second PLL is equipped with a built-in femtosecond NG PLL: 2949.12MHz

For 3932.16MHz: See 8V19N492-39

For 3686.4MHz: See 8V19N491-36

For 2457.6MHz: See 8V19N490-24 and 8V19N491-24

For 1966.08MHz: See 8V19N490-19

There are six output channels, totaling 19 outputs, organized as follows:

Four JESD204B channels (device clock and SYSREF output), with two-channel, four-channel and six-channel outputs

A clock channel has two outputs

One VCXO output

Configurable integer clock divider

The supported clock output frequencies include :2949.12, 1474.56, 983.04, 491.52, 245.76, and 122.88

The low-power LVPECL/LVDS output supports configurable signal amplitudes, DC and AC coupling, as well as LVPECL and LVDS line termination technologies

Phase delay circuit

Clock phase delay, 256 steps, 339ps, range 0 to 86.466ns

Independent SYSREF phase delay, 8-step 169ps

Additional independent SYSREF precision phase delay, 25ps step

Global SYSREF signal delay, 256 steps, 339ps, range 0 to 86.466ns

A redundant input clock architecture with four inputs, including:

Input activity monitoring

Manual and automatic, fault-triggered clock selection modes

Priority control clock selection

Digital hold and non-interruptible switch

The differential input accepts LVDS and LVPECL signals

The generation modes of SYSREF include the internal and external trigger modes of JESD204B

Power supply voltage :3.3V

SPI and control I/O voltage :1.8V/3.3V(optional)

Package: 11mm x 11mm 100-CABGA

The 8V19N490BBDGI has been optimized to provide the outstanding phase noise performance required for the implementation of GSM, WCDMA, LTE and LTE-A radio boards. The 8V19N490B supports JESD204B subclass 0 and 1 clocks.

Typical applications

Wireless infrastructure applications: GSM, WCDMA, LTE, LTE-A

An ideal clock driver for jitter sensitive ADC and DAC circuits

Low phase noise clock generation

Ethernet cable card

Radar and Imaging

Instrumentation and medical care

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