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The 8P391208NLGI is a low additional jitter 2:8 buffer with universal differential output designed to take one or two reference clocks, select between them using pin selection, and produce up to eight outputs at the same frequency as the reference. The 8P391208NLGI supports two output groups, each with its own power supply. All outputs in a memory cell will generate the same output frequency, and each memory cell can independently control the output type or output enable.

Main features

Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS reference clocks

Accept input frequencies within the range of 1PPS (1Hz) to 700MHz (up to 1GHz when configured in HCSL output mode at 3.3V)

Through pin selection, choose which of the two input clocks is used as the reference clock for which memory

Generate 8-channel differential output

Differential output can be selected as LVPECL, LVDS, CML or HCSL

The CML mode supports two different voltage oscillations

The differential output supports frequencies from 1PPS to 700MHz (up to 1GHz when configured in HCSL output mode at 3.3V).

The outputs are arranged in 2 groups, with 4 outputs in each group

Each group supports an independent power supply of 3.3V, 2.5V or 1.8V

Controlled by a 3-level input pin

Input the multiplexing selection control pin

For all core voltages, the tolerance of the control input is 3.3V

The output noise base at 156.25MHz is -153 DBC /Hz

Core supply voltages of 3.3V, 2.5V or 1.8V

Ambient operating temperature: -40°C to +85°C

Lead-free (RoHS 6) packaging

Typical application fields of 8P391208NLGI

Server/storage system: High-precision clock allocation.

Industrial and communication equipment: Timing management for FPgas and ASics.

Medical electronics: Signal processing systems with low jitter requirements.

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