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The AD9642BCPZ-250 is a 14-bit analog-to-digital converter (ADC) with a sampling rate as high as 250 MSPS, designed to provide solutions for low-cost, small-sized, wide-bandwidth, and multi-functional communication applications. This ADC core adopts a multi-level, differential pipeline architecture and integrates output error correction logic. Each ADC has a wide bandwidth input and supports various input ranges selectable by the user. Integrated reference voltage sources can simplify the design. The duty cycle stabilizer (DCS) can be used to compensate for the fluctuations in the duty cycle of the ADC clock, enabling the converter to maintain excellent performance.

Main characteristics

The AD9642BCPZ-250 has the following main features:

Signal-to-noise ratio (SNR) : 71.0 dBFS (185 MHz input, 250 MSPS)

Spurious dynamic range (SFDR) : 83 dBc (185 MHz input, 250 MSPS)

Input noise: -152.0 dBFS/Hz (200 MHz, -1 DBFS input, 250 MSPS)

Total power consumption: 390 mW (250 MSPS)

1.8V power supply voltage

LVDS (ANSI-644 level) output

1 to 8 integer input clock divider (maximum input frequency 625MHz)

The sampling rate can reach up to 250 MSPS at most

The intermediate frequency sampling frequency can reach up to 350 MHz at most

Internal reference voltage source of ADC

Flexible analog input range: 1.4V p-p to 2.0V p-p (nominal value 1.75V p-p)

Furthermore, the AD9642BCPZ-250 is applicable to the following application fields:

- Communication

Diversity radio system

Multimode digital receiver (3G)

TD-SCDMA, WiMax, WCDMA

CDMA2000, GSM, EDGE, LTE

- I/Q demodulation system

Intelligent antenna system

General-purpose software-defined radio

Ultrasonic equipment

Broadband data application

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