sales@hkmjd.com
Service Telephone:86-755-83294757
Trade Name:RF Receiver
Brand:ADI
Particular Year:25+
Package:LFCSP-56
Delivery Date:New and Original
Stock: 3000pcs
AD6641BCPZRL7-500: 250MHz Bandwidth Digital Pre-Distortion (DPD) Observation Receiver, LFCSP-56
Model: AD6641BCPZRL7-500
Package: LFCSP-56
Type: RF Receiver - Digital Pre-Distortion (DPD) Observation Receiver
The AD6641BCPZRL7-500 is a 250 MHz bandwidth digital pre-distortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multi-mode back-end, allowing users to Retrieve data stored in the integrated FIFO memory. It offers excellent dynamic performance and low power consumption for telecom applications such as digital pre-distorted observation paths requiring wider bandwidth. All necessary functions are integrated on the chip, including a sample holder and reference voltage source, providing a complete signal conversion solution.
AD6641BCPZRL7-500 Product Features:
Signal-to-noise ratio (SNR): 65.8 dBFS (fIN up to 250MHz, 500 MSPS)
Effective Number of Bits (ENOB): 10.5 bits (fIN up to 250 MHz, 500 MSPS, -1.0 dBFS)
Spurious-free dynamic range (SFDR): 80 dBc (fIN up to 250 MHz, 500 MSPS, -1.0 dBFS)
Excellent linearity
DNL = ±0.5 LSB (typical); INL = ±0.6 LSB (typical)
Integrated 16k × 12 FIFO
FIFO readback option
12-bit parallel CMOS (62.5 MHz)
6-bit DDR LVDS interface
SPORT (62.5 MHz)
SPI (25 MHz)
High-speed synchronisation capability
1 GHz full power analogue bandwidth
Integrated input buffer
On-chip reference voltage source, no external decoupling required
Low power consumption
695 mW (500 MSPS)
Programmable input voltage range
1.18 V to 1.6 V, 1.5 V nominal
Powered by 1.9 V analogue and digital supplies
1.9 V or 3.3 V SPI and SPORT operating modes
Clock duty cycle stabiliser
Integrated data clock output with programmable clock and data alignment function
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