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The AD9528BCPZ is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator, which can be used for multi-device synchronization. Its technical parameters are as follows:

PLL: With bypass

Input: CMOS, HSTL, LVDS

Output: HSTL, LVDS

Number of circuits: 1

Ratio - Input: Output: 2:14

Differential - Input: Output: Yes/Yes

Frequency - Maximum: 1.25GHz

Frequency divider/frequency doubler: Yes/No

Voltage - Power supply: 3.135V to 3.465V

Operating temperature: -40°C to 85°C

Installation type: Surface mount type

Device packaging: 72-LFCSP-VQ (10x10)

The first-stage phase-locked loop (PLL) (PLL1) achieves input reference voltage conditioning by reducing the jitter of the system clock. The second-level PLL (PLL2) provides a high-frequency clock, enabling lower integration jitter and lower wideband noise from the clock output driver. The external VCXO provides the low-noise reference voltage required by PLL2 to meet the demanding phase noise and jitter requirements and achieve acceptable performance. The tuning frequency range of the on-chip VCO is from 3.450 GHz to 4.025 GHz. The integrated SYSREF generator outputs single, N or continuous signals and synchronizes them with the PLL1 and PLL2 outputs to align The Times of multiple devices.

The AD9528BCPZ can generate six outputs with a maximum frequency of 1.25 GHz (Output 0 to Output 3, Output 12 and Output 13), as well as eight outputs with a maximum frequency of up to 1 GHz.

Application scenarios

High-performance wireless transceiver

LTE and multi-carrier GSM base stations

Wireless and broadband infrastructure

Medical instruments

Provide clocks for high-speed ADC, DAC, DDS, DDC, DUC and MxFE; Supports JESD204B/JESD204C

Low-jitter and low-phase noise clock distribution

Automatic test equipment (ATE) and high-performance instruments and meters

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