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The AD9571ACPZPEC device features a multi-output clock generator function and is equipped with a dedicated PLL core, which is optimized for Ethernet line card applications. The integer N PLL design is based on ADI's mature high-performance, low-jitter frequency synthesizer product series to ensure high network performance. This device is also suitable for other applications with strict requirements for phase noise and jitter.

Main characteristics

Fully integrated with the VCO/PLL kernel

At 156.25 MHz, jitter value: 0.17 ps root mean square value (1.875 MHz to 20 MHz)

At 125 MHz, jitter value: 0.41 ps root mean square value (12 kHz to 20 MHz)

Input crystal oscillator or clock frequency: 25 MHz

For the preset frequency division ratios of 156.25 MHz, 33.33 MHz, 100 MHz and 125 MHz

Optional output formats include LVPECL or LVDS

Integrated loop filter

6-channel reference clock output

The rate is configured through the binding pin

Space-saving 6mm × 6mm, 40-pin LFCSP package

Power consumption: 0.48W (LVDS working mode)

Application field

The AD9571ACPZPEC is widely used in devices such as Ethernet line cards, switches and routers that require low jitter and low phase noise clock generation. It also works with SCSI, SATA and PCI express support devices such as ‌

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