sales@hkmjd.com
Service Telephone:86-755-83294757
Trade Name:LMK03318RHSR
Data Manual:LMK03318RHSR.pdf
Brand:TI
Particular Year:23+
Package:WQFN-48
Delivery Date:New and Original
Stock: 2500pcs
The LMK03318RHSR device is an ultra-low-noise PLLATINUM™ clock generator with one fractional-N frequency synthesizer with integrated VCO, flexible clock distribution and fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, thus reducing BOM cost and board area and improving reliability by replacing multiple oscillators and clock distribution devices. The ultra-low jitter reduces bit-error rate (BER) in high-speed serial links.
For the PLL, a differential clock, a single-ended clock, or a crystal input can be selected as the reference clock. The selected reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input frequency. The VCO frequency can be tuned between 4.8 GHz and 5.4 GHz. The PLL offers the flexibility to select a predefined or user-defined loop bandwidth, depending on the needs of the application. The PLL has a post-divider that can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.
Features
• Ultra-Low Noise, High Performance
– Jitter: 100-fs RMS Typical, FOUT > 100 MHz
– PSNR: –80 dBc, Robust Supply Noise Immunity
• Flexible Device Options
– Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or Any Combination
– Pin Mode, I2C Mode, EEPROM Mode
– 71-Pin Selectable Pre-programmed Default Start-Up Options
• Dual Inputs With Automatic or Manual Selection
– Crystal Input: 10 to 52 MHz
– External Input: 1 to 300 MHz
• Frequency Margining Options
– Fine Frequency Margining Using Low-Cost Pullable Crystal Reference
– Glitchless Coarse Frequency Margining (%) Using Output Dividers
• Other Features
– Supply: 3.3-V Core, 1.8-V, 2.5-V, or 3.3-V Output Supply
– Industrial Temperature Range (–40ºC to 85ºC) SPACER
Applications
• Switches and Routers
• Network and Telecom Line Cards
• Servers and Storage Systems
• Wireless Base Station
• PCIe Gen1, Gen2, Gen3, Gen4
• Test and Measurement
• Broadcast Infrastructure
Model
Brand
Package
Quantity
Describe
TI
14-TSSOP
3000
Programmable 1-PLL clock synthesizer and jitter eliminator with 2.5V and 3.3V outputs
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