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AD9690BCPZ-500

14-bit, 500Msps JESD204B ADC

Main advantages:

Wide full power bandwidth, support up to 2 GHz IF signal sampling

Providing a programmable input buffer simplifies filter design and implementation.

Two integrated wideband decimation filters and numerical control oscillator (NCO) modules support multi-band receivers.

Flexible serial port interface (SPI) controls a variety of product features and functions to meet specific system requirements.

Programmable fast overrange detection.

9 mm x 9 mm, 64 pin LFCSP.

Description:

The AD9690 is a 14-bit, 500 Msps/1 GSPS analog-to-digital converter (ADC). The device has a built-in on-chip buffer and sample-hold circuit designed specifically for low power consumption, small size and ease of use. The device is designed for broadband analog signal sampling up to 2 GHz. The AD9690 is optimized for wide input bandwidth, high sampling rates, excellent linearity and low power consumption in a small package.

The ADC core uses a multistage, differential pipeline architecture with integrated output error correction logic. The ADC has a wide bandwidth input and supports a variety of input ranges that the user can select. Integrated reference voltage source simplifies design.

Features:

JESD204B (subclass 1) encodes serial digital output

Total power consumption at 500 GSPS: 1.5W (default setting)

SFDR = 85 dBFS (340 MHz), 80 dBFS (1 GHz)

SNR = 65.3 dBFS (340 MHz, AIN = −1.0 dBFS); 61.4 dBFS (1 GHz)

ENOB = 10.8 bits (10 MHz)

DNL = ±0.5 LSB

INL = ±2.5 LSB

Noise density = -154 dBFS/Hz (1 GSPS)

Dc power supply: 1.25V, 2.5V and 3.3V

Loss-free code

ADC internal reference voltage source

Applications:

communication

Multi-band, multi-module digital receiver 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE

General software radio

Ultra wideband satellite receiver

Instrument and meter

radar

Signals Intelligence (SIGINT)

DOCSIS 3.0 CMTS upstream receiving path

HFC digital reverse path receiver