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The AD9689BBPZ-2000 is a 14-bit dual 2GSPS analog-to-digital converter (ADC).
AD9689BBPZ-2000, a 14-bit dual-channel 2GSPS analog-to-digital converter (ADC)Product Introduction:The AD9689 is a dual-channel, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has a built-in on-chip buffer and sample-hold circ…
AD9689BBPZ-2000, a 14-bit dual-channel 2GSPS analog-to-digital converter (ADC)
Product Introduction:
The AD9689 is a dual-channel, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has a built-in on-chip buffer and sample-hold circuit designed specifically for low power consumption, small size and ease of use. The product is designed to support communication applications, enabling direct sampling of broadband wide analog signals up to 5 GHz. The ADC input bandwidth of −3 dB is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rates, excellent linearity and low power consumption in a small package.
The dual-channel ADC core uses a multistage, differential pipeline architecture with integrated output error correction logic. Each ADC has a wide bandwidth input and supports a wide range of input options for the user. Integrated voltage reference source simplifies design considerations. Analog input and clock signal are differential input signals.
In addition to the DDC module, the AD9689 has additional features that simplify the automatic gain control (AGC) function of the communications receiver. The programmable threshold detector can monitor the input signal power using the fast detection control bit in the ADC's register 0x0245.
Users can set the JESD204B subclass 1's high-speed serial output to a variety of single -, dual -, four-channel, and eight-channel configurations, depending on the DDC configuration of the receiving logic device and the acceptable channel rate. SYSREF± and SYNCINB± input pins support multi-device synchronization.
The AD9689 has a flexible turn-off option that dramatically reduces power consumption when needed. All of these features can be programmed through a three-wire serial port interface (SPI).
Product aggregation:
9 GHz wide input −3 dB bandwidth supports direct radio frequency (RF) signal sampling of about 5 GHz.
Four integrated, wideband decimation filters and NCO modules support multi-band receivers.
Fast NCO switch enabled by GPIO pin.
SPI controls a variety of product features and functions to meet specific system requirements.
Programmable fast overrange detection and signal monitoring.
On-chip temperature diode for system thermal management.
12 mm x 12 mm, 196 pin BGA package.
Pin, package, function and memory mapping compatible with AD9208 14-bit, 3.0 GSPS, JESD204B dual-channel ADCs.
Applications:
Diversity multiband and multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA and GSM, LTE, LTE-A
Electronic test and measurement systems
Phased array radar and electronic warfare
DOCSIS 3.0 CMTS upstream receiving path
HFC digital reverse path receiver
Time:2024-11-20
Time:2024-11-20
Time:2024-11-20
Time:2024-11-20
Contact Number:86-755-83294757
Enterprise QQ:1668527835/ 2850151598/ 2850151584/ 2850151585
Business Hours:9:00-18:00
E-mail:sales@hkmjd.com
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