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SI5383A-D10188-GMR is a high-performance network synchronous clock IC, belonging to Si538x series, which is designed for telecom, data centre, industrial communication and other applications requiring high-precision clock synchronization. Packaged in an LGA-56 package, the chip supports multiple clock outputs with low jitter and high stability, and is suitable for 5G base stations, optical modules, SDH/SONET equipment, and other scenarios.

SI5383A-D10188-GMR Key Features

High-precision clock synthesis and jitter removal

Supports 7 independent clock outputs (CML/HCSL/LVDS/LVPECL/LVCMOS level selectable)

Output frequency up to 718.5 MHz, input frequency up to 750 MHz (LVCMOS)

Ultra-low jitter performance (<100 fs RMS) for high-speed SerDes applications

Flexible configuration and low power design

Programmable PLL and frequency divider to support arbitrary frequency synthesis

Ultra-low supply voltage of 1.71V ~ 1.89V, typical operating current 245 mA

Sleep mode power consumption optimised for energy efficient applications

Industrial Grade Reliability

Operating temperature range: -40°C to +85°C5

RoHS-compliant, moisture-sensitive class MSL

LGA-56 package (8 x 8 mm) for high-density PCB designs

Network Synchronisation

Supports IEEE 1588 Precision Time Protocol (PTP)

Suitable for network synchronisation standards such as SyncE, OTN, CPRI, etc.

Applications of SI5383A-D10188-GMR

- Synchronised Ethernet (SyncE) ITU-T G.8262 EEC Options 1 and 2

- ITU-T G.8273.1 Telecom Master Clock (T-GM) as defined by ITU-T G.8273.1

- Telecom Boundary Clock and Slave Clock (T-BC, T-TSC) as defined in ITU-T G.8273.2

- IEEE 1588 (PTP) slave clock synchronisation

- Layer 3/3E, G.812, G.813, GR-1244, GR-253 Network Synchronisation

- 1 Hz/1 PPS Clock Multiplier

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