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The ZL30702LDG6 is an Ethernet clock synthesizer IC featuring high performance and low jitter for a wide range of communication and networking devices.The ZL30702LDG6 provides two independent timing channels and combines hardware and software platforms including the IEEE 1588-2008 precision time stack and synchronisation algorithms. The device provides a highly integrated synchronous Ethernet/IEEE 1588 timing solution with one-third the jitter of the previous generation and a 40% smaller footprint, making it ideal for timing card applications in systems that need to support 10G/40G and 100G physics.

Specifications (ZL30702LDG6)

Primary application: Ethernet  

Input: CML, HCSL, LVDS, LVPECL  

Output: CML, LVCMOS  

Number of circuits: 4  

Ratio - Input:Output: 5:8  

Differential - Input:Output: Yes/Yes  

Operating Temperature: -40°C ~ 85°C  

Mounting Type: Surface Mount  

Package/Shell: 100-VQFN Dual In-line, Unpadded  

Supplier Device Package: 100-aQFN (10x10) 

Features

Up to two independent clock channels

Fully compliant with EEC (G.8262), SEC (G.813), GR-253 SMC and GR-1244 Stratum 3/3E standards

Frequency accuracy performance for GSM, WCDMAFDD, LTE-FDD base station and small cell applications with target performance less than ± 15 ppb

Frequency performance for ITU-T G.823 and G.824 synchronisation interfaces and G.8261 PNT EEC, PNT PEC and CES interface specifications

Phase synchronisation performance for WCDMA-TDD, TD-SCDMA, CDMA2000, LTE-TDD and LTE-A applications, with a target performance of less than ± 1 µs of phase alignment

Client hold and reference switching between multiple servers

Supports the new ITU-T Packet Clock Recommendations or drafts: g.8263 pec-s, g.8273.2 t-bc, t-tsc, g.8273.4 t-bc-p, t-tsc-p, and t-tsc-a

Excellent jitter performance of 180 fs RMS (12 kHz to 20 MHz) to meet 10G/40G and 100G PHY jitter requirements

Up to four programmable digital PLLs/NCOs with loop bandwidths from 0.1 mHz to 470 Hz, synchronised to any clock rate from 0.5 Hz to 900 MHz

Automatic, non-disruptive reference switching and digital holdover in the event of a reference failure, with initial holdover accuracy better than 0.1 ppb

Feed any input reference via clock, sync (frame pulse), clock/sync pairs

Easy configuration and dynamic programming via SPI/I2C interface

Operates from a single crystal resonator or clock oscillator

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