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The AD6636BBCZ is a (digital) receive signal processor designed primarily for use in direct IF sampling or high sampling baseband radios requiring wide bandwidth input signals. It has been optimised for the demanding filtering requirements of wideband standards such as CDMA2000, UMTS and TD-SCDMA. The device is primarily intended for use in radio systems employing IF sampling ADCs or baseband sampling ADCs.

The AD6636BBCZ features the following signal processing stages: a frequency converter, a five-stage cascaded integrated comb filter, two sets of cascaded fixed-coefficient finite impulse response (FIR) and half-band filters, three cascaded programmable coefficients sum-of-products FIR filters, an interpolating half-band filter (LHB), and a digital automatic gain control (AGC) module. The device supports multiple modes of synchronising data to and from the chip to allow flexible interfacing with a variety of digitizers. Programming and control is accomplished through a serial or miniport interface.

The AD6636BBCZ contains a fractional clock multiplier that uses the ADC clock to generate a digital downconverter master clock up to 200 MHz. Using this internal phase-locked loop (PLL), the digital clock rate can be optimised for high-quality digital signal extraction and filtering, regardless of the inverter sampling rate. Three 16-bit parallel output ports are suitable for high data rate 3G applications. The output rate can also be further increased using on-chip interpolation half-band filters, while still allowing efficient filtering. In addition, each channel has a digital AGC for adjusting the output data.

Features - AD6636BBCZ

Six independent wideband processing channels

Processes six wideband carriers (UMTS, CDMA2000, TD-SCDMA, etc.)

Four single-ended or two LVDS parallel input ports (16-bit linear plus 3-bit exponential), and

Operating frequency of 150 MHz

Supports 300 MHz input using external interface logic

Three 16-bit parallel output ports operating up to 200 MHz

Real or complex signal input ports

Quadrature and DC correction for complex signal inputs

Supports output rates up to 34 MSPS

Input ports with RMS/peak power monitoring

Programmable attenuator control for external digital variable gain amplifier (DVGA)

Three programmable coefficient FIR filters per channel

One interpolating half-band filter per channel

Applications - AD6636BBCZ

Multi-carrier, multi-mode digital receivers

GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA, WiMAX

Micro and pico cellular systems, software radios

Broadband data applications

Instruments and Test Equipment

Wireless Local Loop

In-building wireless telephony

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