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The CY15B102QN-50LHXI is a 1.8V synchronous pipelined SRAM equipped with the QDR II architecture. the QDR II architecture consists of two separate ports: a read port and a write port, for accessing the memory array. The read port has a dedicated data output to support read operations and the write port has a dedicated data input to support write operations. the QDR II architecture has separate data inputs and data outputs to completely eliminate the need for a "turnaround" data bus that exists with normal I/O devices. Access to each port is via a common address bus. Read and write addresses are latched on the alternate rising edge of the input (K) clock. Access to the QDR II read and write ports is completely independent. To maximise data throughput, both read and write ports are equipped with DDR interfaces. Each address position is associated with two 8-bit words (CY7C1510KV18), 9-bit words (CY7C1525KV18), 18-bit words (CY7C1512KV18) or 36-bit words (CY7C1514KV18) which enter or leave the device in sequence. Since data can be transferred to and from the device on each rising edge of the two input clocks (K and K and C and C), memory bandwidth is maximised and system design is simplified by eliminating bus turnover.

CY15B102QN-50LHXI Product Attributes

Product Type: Static Random Access Memory

Memory capacity: 72 Mbit

Organisation: 2 M x 36

Access time: 450 ps

Maximum clock frequency: 250 MHz

Interface type: Parallel

Supply voltage - max: 1.9 V

Supply voltage - min: 1.7 V

Supply current - max: 790 mA

Minimum operating temperature: - 40 C

Max. operating temperature: + 85 C

Mounting style: SMD/SMT

Package / Case: FBGA-165

Storage type: QDR

Humidity Sensitivity: Yes

Product Type: SRAM

Family: CY7C1514KV18

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