sales@hkmjd.com
Service Telephone:86-755-83294757
Trade Name:SRAM Memory
Brand:INFINEON
Particular Year:25+
Package:100-TQFP
Delivery Date:New and Original
Stock: 2000pcs
CY7C1373KV33-100AXC is 3.3 V, 512K × 36/1M × 18 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. The CY7C1373KV33-100AXC is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with databeing transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.
Features Of CY7C1373KV33-100AXC
No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data is transferred on every clock
Pin-compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need to use OE
Registered inputs for flow through operation
Byte write capability
3.3 V/2.5 V I/O power supply (VDDQ)
Fast clock-to-output times
6.5 ns (for 133 MHz device)
Clock enable (CEN) pin to enable clock and suspend operation
Synchronous self-timed writes
Asynchronous output enable
Available in JEDEC-standard Pb-free 100-pin TQFP packages
Three chip enables for simple depth expansion
Automatic power-down feature available using ZZ mode or CE deselect
Burst capability – linear or interleaved burst order
Low standby power
On chip Error Correction Code (ECC) to reduce Soft Error Rate (SER)
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