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The PCA9617ATPZ is a CMOS integrated circuit that provides level-switching between low-voltage (0.8 V to 5.5 V) and higher-voltage (2.2 V to 5.5 V) ultra-fast-mode (Fm+) I²C bus or SMBus applications. While retaining all operating modes and functions of the I²C bus system during level-switching, the device also allows for the expansion of the I²C bus by providing bi-directional buffering for the data (SDA) and clock (SCL) lines to allow for the expansion of the I²C bus to enable two buses of 540 pF at 1 MHz and up to 4000 pF at lower speeds. The use of the PCA9617A enables the system designer to isolate the bus voltage and capacitance in half. the SDA and SCL pins are overvoltage tolerant and high impedance when the PCA9617A is not powered on.

Key Features

2-channel, bi-directional buffers isolate capacitors, allowing 540 pF capacity on both sides of the device at 1 MHz and supporting up to 4000 pF capacity at lower speeds.

Voltage level switching: from 0.8 V to 5.5 V and from 2.2 V to 5.5 V

PCA9517A footprint and feature replacement in fast mode

Port A voltage range from 0.8 V to 5.5 V (normal level)

Port B voltage range of 2.2 V to 5.5 V (static offset level)

5 V tolerant I2C bus and enable pins

Clock frequency from 0 Hz to 1000 kHz (maximum system operating frequency may be less than 1000 kHz due to delays added by the transponder)

Effective high repeater enable input referenced to VCC(B)

Open-drain input/output

Latchless operation

Supports arbitration and clock extension through repeaters

Supports standard, fast, and ultra-fast mode I2C bus devices, SMBus (standard and high power modes), PMBus, and multiple controllers

Power-down high impedance I2C bus pins

ESD protection: over 5500 V HBM per JESD22-A114, over 1000 V CDM per JESD22-C101

Lockout test in excess of 100 mA per JEDEC standard JESD78

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