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Shenzhen Mingjiada Electronics Co., Ltd.[Recycling] TI ARM926EJ-S Microprocessor IC OMAPL137DZKBA3 OMAP-L1x 1-core, 32-bit 375MHz 256-BGA(17x17).

Product Details:

The OMAPL137DZKBA3's dual-core architecture combines the high-performance TMS320C674x DSP core and the ARM926EJ-S core, offering the benefits of DSP and Reduced Instruction Set Computer (RISC) technology. The device is a 32-bit RISC processor core that executes 32-bit or 16-bit instructions and processes 32-bit, 16-bit or 8-bit data. The core has a pipelined design that allows all parts of the processor and memory system to run continuously. the ARM core has a coprocessor 15 (CP15), protection module, data and programme memory management unit (MMU) with table lookup bypass buffers. the ARM core has a separate 16KB instruction cache and 16KB data cache. both memory blocks are virtual indexed. The ARM core has a separate 16KB instruction cache and 16KB data cache, both of which are four-way associative using virtual indexed virtual tokens (VIVT).The ARM core also has 8KB of RAM (vector tables) and 64KB of ROM.

Features and Benefits

Software Support

TI DSP/BIOS

Chip Support Library and DSP Library

Dual-core SoCs

375- and 456-MHz ARM926EJ-S RISC MPUs

375- and 456-MHz C674x VLIW DSPs

ARM926EJ-S Cores

32-bit and 16-bit (Thumb®) instructions

DSP Instruction Extensions

Single-cycle MAC

ARM® Jazelle® technology

Embedded ICE-RT™ for real-time debugging

ARM9™ memory architecture

16KB Instruction Cache

16KB Data Cache

8KB RAM (vector table)

64KB ROM

C674x Instruction Set Features

Superset of C67x+ and C64x+ ISAs

Up to 3648 MIPS and 2736 MFLOPS for C674x

Byte addressable (8-bit, 16-bit, 32-bit and 64-bit data)

8-bit overflow protection

Bit field extract, set, clear

Normalisation, Saturation, Bit Counting

Compact 16-bit instructions

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