sales@hkmjd.com
Service Telephone:86-755-83294757
Trade Name:TigerSHARC Embedded Processor
Brand:ADI
Particular Year:25+
Package:BGA-576
Delivery Date:New and Original
Stock: 2000pcs
The ADSP-TS201SABPZ050 is one of the newest devices in the TigerSHARC processor family. ADI's TigerSHARC processors are targeted at a wide range of signal processing applications that rely on multiple processors working together to perform compute-intensive real-time functions, and are ideally suited for use in the video and communications markets, including 3G cellular and broadband wireless base stations, as well as defence, medical imaging and industrial instrumentation. The ADSP-TS201SABPZ050 features a static superscalar architecture that combines RISC, VLIW and standard DSP functionality. Inherent support for fixed-point and floating-point data types, coupled with leading-edge multiprocessing capabilities, enables the TigerSHARC processor to deliver unrivalled DSP performance. At a clock frequency of 600MHz, the ADSP-TS201SABPZ050 delivers industry-high 16-bit fixed-point performance and 32-bit floating-point performance.The ADSP-TS201SABPZ050 features a 1024-point complex FFT time of 16.8µs and delivers 1500 MFLOPs/W performance.
ADSP-TS201SABPZ050 Performance.
-High-performance 600MHz, 1.67ns instruction rate DSP core
Executes eight 16-bit MAC instructions with 40-bit accumulation or two 32-bit MAC instructions with 80-bit accumulation per cycle.
Executes 6 single-precision floating-point operations or 24 16-bit fixed-point operations per cycle (3.6 GFLOPS or 14.4 GOPS performance)
Dual-cycle, interlocked execution channels
-Parallelism allows execution of up to four 32-bit instructions per cycle
The ADSP-TS201S is available in a low-cost 25mm x 25mm BGA package.
ADSP-TS201SABPZ050 Features:
Static superscalar architecture supporting 1-, 8-, 16- and 32-bit fixed- and floating-point data processing
High performance 600 MHz, 1.67 ns instruction rate DSP core
24 Mb of on-chip embedded DRAM, internally organised into six libraries with support for user-defined partitioning
Enhanced communications instruction set to support wireless infrastructure applications, bringing complete baseband processing capability to TigerSHARC processors
14-channel zero-overhead DMA controller
Four 128-bit wide internal buses for total memory bandwidth of 38.4 Gb/s
Software radio design enables a single platform to support multiple wireless communication standards
Two computing modules supporting single instruction multiple data (SIMD) operations, each with a built-in ALU, multiplier, converter, and 32-word register file
Supports assembly and C programming
Temperature range: -40°C to +85°C
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