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The TMS320VC5510AZAV1 fixed-point digital signal processor is based on the C55x DSP CPU core. The device uses the C55x™DSP architecture to achieve high performance and low power consumption by increasing parallel capability and focusing on reducing power consumption.

Product: TMS320VC5510AZAV1

Core: C55x

Package: NFBGA-240

Features:

High performance, low power, fixed-point TMS320C55x™; Digital Signal Processor (DSP)

Instruction cycle time: 6.25/5ns

Clock rate: 160/200MHz

Execute one or two instructions per cycle

Double multiplier (up to 40,000 multiply and add operations per second (MMACS))

Two arithmetic/logic units

An internal program bus

Three internal data/operand read buses

Two internal data/operand writes to the bus

Instruction cache (24K bytes)

160K of 16-bit on-chip RAM, including

Eight blocks of 4K × 16-bit dual-access RAM (DARAM) (64K bytes)

32 blocks of 4K × 16-bit Single Access RAM (SARAM) (256K bytes)

32-bit external memory interface (EMIF) with connection

Asynchronous Static RAM (SRAM)

Asynchronous EPROM

Synchronous DRAM (SDRAM)

Synchronous Burst SRAM (SBSRAM)

16K x 16-bit on-chip ROM (32K bytes)

8 M x 16 bit maximum addressable external memory space

Programmable low power control of six device function areas

On-chip peripherals

Two 20-bit timers

Six-channel Direct Memory access (DMA) controller

Three multi-channel buffered Series Ports (McBSP)

16-bit Parallel Enhanced Host Port Interface (EHPI)

Programmable digital phase-locked loop (DPLL) clock generator

Eight universal I/O (GPIO) pins and specialized Universal Output Pins (XF)

Simulation logic based on scan on chip

IEEE Std 1149.1 (JTAG) boundary scan logic

240-pin MicroStar BGA™; (Ball Grid Array) (GGW suffix)

240-pin MicroStar BGA™; (Ball grid Array) (ZGW suffix) 【 Lead-free 】

3.3V I/O supply voltage

Core power supply voltage: 1.6V

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