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The ZL30640ALDG1 is a feature-rich time buffer with two separate DPLLs, up to 10 inputs and 20 outputs, and embedded Time (eToD) features. The time signal fan-out solution is ideal for use with timing cards or line card timing ics for 5G telecommunications systems.

ZL30640ALDG1 features:

Highlights

Time signal fanout

One DPLL for buffer channel and second DPLL for input phase/frequency measurement

Time signal conversion between Ref-Sync pair and embedded Sync signals

Time signal phase/frequency measurement

Inputs: up to 10, differential or single-ended with any frequency from 1 kHz to 1250 MHz

Outputs: up to 10 differential, up to 20 CMOS with any frequency 0.5 Hz to 500 MHz

Core power consumption <0.9W

General Features

Automatic self-configuration at power-up from internal Flash memory, 7 configurations

Input-to-output alignment <100 ps

Fast Ref-Sync locking for frequency and 1PPS phase alignment with lower-cost oscillator

Easy-to-configure design requires no external VCXO or loop filter components

5 GPIO pins with many possible behaviors, each REF can be GPI, each OUT can be GPO

SPI or I2C processor Interface

1.8V and 3.3V core VDD voltages

Easy-to-use evaluation/programming software

MiToDSync 1-wire time-of-day interface in/out

MiToDBasic 3-wire time-of-day interface out

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