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[DSP] TMS320DM6437ZWT4 Digital Media Processor Based on TI DaVinci Technology

[DSP] TMS320DM6437ZWT4 Digital Media Processor Based on TI DaVinci Technology

Source:our siteTime:2024-10-15Views:

The TMS320DM6437ZWT4 device is a 400MHz 32-bit fixed-point DSP (DaVinci(TM)) processor developed by TI specifically for high-performance, low-cost video applications.

The TMS320DM6437ZWT4 device is a 400MHz 32-bit fixed-point DSP (DaVinci(TM)) processor developed by TI specifically for high-performance, low-cost video applications.

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Specifications of TMS320DM6437ZWT4:

Core: C64x

Type: Fixed point

Interface: HPI, I2C, McASP, McBSP, PCI, UART, 10/100 Ethernet MAC

Clock rate: 400MHz

Non-volatile memory: ROM (64kB)

On-chip RAM: 240kB

Voltage - I/O: 1.8V, 3.3V

Voltage - core: 1.05V, 1.20V

Operating temperature: 0°C ~ 90°C (TJ)

Mounting type: Surface mount type

Package/housing: 361-LFBGA

Supplier Package: 361-NFBGA (16x16)


The TMS320DM6437 has the following features:

The TMS320C64x+ DSP core adopts TI's 3rd generation ultra-long instruction set structure (Velociti-3), the main frequency can reach 600MHz, supports 8 8-bit or 4 16-bit parallel MAC operations, and the peak processing capacity is up to 4800MIPS. Real-time processing of 8-way CIF or 3-way D1 format H.264 coding algorithm.

Adopt 2-level Cache memory architecture, there are 32K bytes of RAM/ cache-configurable 1-level program memory L1P on the chip, 48K bytes of RAM + 32K bytes of RAM/ cache-configurable 1-level data memory L1D, And 128K bytes of RAM/Cache configurable 2-level program/data memory L2, memory architecture is more flexible and reasonable, conducive to improving the throughput of image processing code/data.

The 64 channel enhanced DMA controller EDMA3 supports the transmission of complex data types, which is conducive to the efficient transmission and format conversion of image data.

Rich external memory interface: a dedicated 32-bit, 200MHz, 256M byte addressing space DDR2 memory interface is used to interface high-speed, large-capacity DDR2 memory to store code and data; An 8-bit, 64M byte addressing space asynchronous memory interface is used to interface 8-bit Nor Flash or Nand Flash to store solidified code.

Rich on-chip peripherals: a dedicated single-channel video input interface, which can easily interface with various digital video input standards, and also has the commonly used video preprocessing function; A dedicated single channel video output interface, can provide a variety of analog video output standards, can also provide a variety of digital video output standard interface, and before the video output, but also support multiple video window management and overlay text data on the video screen; A multi-channel audio serial port can seamlessly interface audio Codec devices to achieve analog video signal input/output; An I2C bus, seamless interface video decoder/encoder and audio Codec control port, easy to achieve sound/video codec control; 32-bit PCI bus, easy to interface with PC, to achieve multi-board parallel work. 10/100M Ethernet MAC, easy to achieve embedded video networking requirements; 16-bit HPI interface to facilitate the implementation of dual processor video processing system with master/slave structure.


It can be seen from the above that DM6437 is very suitable for being the main processor of single channel video processing system. In order to make the DM6437 suitable for multi-channel video surveillance system, the data of multiple video channels need to be combined and then input through the DM6437 on-chip video input interface.


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