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Instructions:

TMS32C5517AZCHA20R fixed-point digital signal processor (DSP) is based on TMS320C55x DSP generation CPU processor core. The C55x DSP architecture increases parallel capabilities and focuses on power-saving design for improved performance and reduced power consumption.

The CPU supports an internal bus structure that includes a program bus, a 32-bit data read bus, two 16-bit data read buses, and two 16-bit data write buses. The device also has additional buses specifically for peripherals and DMA operations. These buses can perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with four channels, providing data movement for 16 separate channel contexts with no CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, which is parallel to and independent of CPU operation.

Product: TMS32C5517AZCHA20R

Clock frequency: 75 MHz

Package: NFBGA-196

Features:

Core

High performance, low power TMS320C55x fixed point digital signal processor

13.33ns to 5ns command cycle time

Clock rate: 75MHz to 200MHz

Execute one or two instructions per cycle

Two product accumulation units (up to 450 million product accumulation operations per second [MMACS])

Two arithmetic and logic units (ALU)

Three internal data or operand read buses and two write buses

Compatible with C55x device software

Industrial temperature equipment is available

320KB of zero wait state on-chip RAM

128KB Zero wait state on-chip ROM (4 pieces 16K x 16-bit)

Tightly coupled FFT hardware accelerator

peripheral

A universal host port interface (UHPI) with a 16-bit multiplexed address or data bus

Master control with three-chip selection and controlled multi-channel Serial port interface (McSPI)

Master and Controlled Multichannel Buffered Serial Port Interface (McBSP)

16-bit and 8-bit external memory interfaces (EMIF) with seamless interfacing to the following devices

3.84375M x 16-bit maximum addressable external memory space (SDRAM or mSDRAM)

Universal Asynchronous Receiver/Transmitter (UART)

Device USB port with integrated 2.0 High speed Physical Layer (PHY)

Direct Memory Access (DMA) controller

Three 32-bit general purpose (GP) timers

Two multimedia cards and secure digital (eMMC, MMC, and SD) interfaces

Serial port Interface (SPI) with four chip options

Master/slave Internal Integrated Circuit (I2C Bus™)

Three interintegrated circuit (IC) sound (I2S bus) modules for data transmission

10-bit 4-input Primary and Secondary Approximation (SAR) ADC

IEEE-1149.1 (JTAG) boundary

Up to 26 GPIO pins (multiplexed with other features)

Power source

Four kern-isolated power domains: analog, RTC, CPU and peripherals, and USB

Four I/O isolated power domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO

1.05V core, 1.8, 2.75 or 3.3V I/O

1.3V core, 1.8, 2.75, or 3.3V I/O

1.4V core, 1.8, 2.75, or 3.3V I/O

clock

Real-time clock (RTC) with crystal input, separate clock domain, and power supply

Software programmable phase locked loop (PLL) clock generator

Boot loader

On-chip ROM boot loader

encapsulation

196 terminal lead-free plastic BGA (Ball Grid Array) package (suffix ZCH), 0.65mm pitch

Applications:

Digital two-way radio

Low power analytics applications (e.g., speech recognition, vision sensing, and fingerprint recognition)

Voice applications (e.g., voice recorders, hands-free kits, and voice enhancement subsystems)

Audio devices (e.g., echo canceling headsets and speakerphones or wireless headsets and microphones)

Portable medical equipment