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On September 10, Rambus announced the industry's first HBM4 controller IP. The HBM4 controller IP is designed to meet the high memory bandwidth demands of next generation artificial intelligence (AI) workloads and high performance computing (HPC).

According to the company's public information, the Rambus HBM4 controller IP supports next-generation HBM memory deployments for cutting-edge AI accelerators, graphics, and HPC applications. The HBM4 controller IP also supports the JEDEC specification of 6.4 gigabits per second (Gbps).

The controller IP is also capable of supporting operations up to 10Gbps, providing a throughput of 2.56 terabytes per second (TB/s) per memory device. The RambusHBM4 controller IP can be paired with a third-party or customer PHY solution to instantiate a complete HBM4 memory subsystem.

In addition, Rambus' HBM4 controller IP comes with a variety of advanced feature sets designed to help designers address complex requirements in applications such as next-generation AI accelerators and graphics processing units (Gpus). These features allow Rambus to continue its market leadership in the HBMIP space and further expand its ecosystem support.

Neeraj Paliwal, senior vice president and general manager of Silicon IP at Rambus, said: "With large language models (LLMS) now over a trillion parameters and growing, overcoming memory bandwidth and capacity bottlenecks is critical to meeting the real-time performance requirements of AI training and reasoning. "As a leading silicon IP provider for AI2.0, we are bringing the industry's first HBM4 controller IP solution to market, helping our customers achieve breakthrough performance in their state-of-the-art processors and accelerators."

Rambus' announcement of the HBM4 controller IP not only marks another major breakthrough in the company's high-bandwidth memory technology, but also provides a strong support for technological innovation in related fields.

Company homepage: www.hkmjd.com