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AD9575ARUZLVD: Dual Output Network Clock Generator (IC PLL CLOCK GEN 25MHZ 16TSSOP)

AD9575ARUZLVD: Dual Output Network Clock Generator (IC PLL CLOCK GEN 25MHZ 16TSSOP)

Source:our siteTime:2025-06-07Views:

The AD9575ARUZLVD is a highly integrated dual-output clock generator, particularly suitable for network timing applications.Its main characteristics are:A fully integrated VCO/PLL kernelRoot mean square jitter: 0.39 ps (12 kHz to 20 MHz, 156.25 MHz)Ro…

The AD9575ARUZLVD is a highly integrated dual-output clock generator, particularly suitable for network timing applications.

Its main characteristics are:

A fully integrated VCO/PLL kernel

Root mean square jitter: 0.39 ps (12 kHz to 20 MHz, 156.25 MHz)

Root mean square jitter: 0.15 ps (1.875 MHz to 20 MHz, 156.25 MHz)

Root mean square jitter: 0.40 ps (12 kHz to 20 MHz, 106.25 MHz)

Root mean square jitter: 0.15 ps (637 kHz to 10 MHz, 106.25 MHz)

Input crystal oscillator frequency: 19.44 MHz, 25 MHz or 25.78125 MHz

For 33.33 MHz, 62.5 MHz

100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz

Outputs of 159.375 MHz, 161.13 MHz, and 312.5 MHz are provided, offering pin-selectable crossover ratios

LVDS/LVPECL/LVCMOS output format

Integrated loop filter

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Introduction

The AD9575ARUZLVD is a highly integrated dual-output clock generator, featuring an on-chip PLL core optimized for network timing. The integer N frequency division PLL design is based on ADI's mature high-performance and low-jitter frequency synthesizer series, which can achieve high performance of line cards. Other applications with strict requirements for phase noise and jitter can also benefit from this device.


The AD9575ARUZLVD PLL section consists of a low-noise frequency and phase detector (PFD), a precision charge pump, a low-phase noise voltage-controlled oscillator (VCO), and a pin-optional feedback and output frequency divider. By connecting an external crystal oscillator, the AD9575ARUZLVD can lock the commonly used network output frequencies to the input reference. The output frequency division ratio and feedback frequency division ratio can be programmed through pins according to the required output rate. The AD9575ARUZLVD does not require an external loop filter, thus saving valuable design time and circuit board space.


The AD9575ARUZLVD is available in a 16-pin, 4.4mm × 5.0mm TSSOP package and can be powered by a single 3.3V supply. The temperature range is from -40 °C to +85°C.


The main specifications of AD9575ARUZLVD are as follows:

PLL: Yes

Main application: PCI Express (PCIe)

Input: Crystal

Output: LVCMOS, LVDS, LVPECL

Number of circuits: 1

Ratio - Input: Output: 1:2

Differential - Input: Output: None/Yes

Frequency - Maximum value: 312.5MHz

Voltage - Power supply: 3V to 3.6V

Operating temperature: -40°C to 85°C

Installation type: Surface mount type

Package/Shell: 16-TSSOP


Application field

The AD9575ARUZLVD clock generator is suitable for a variety of applications, including: GbE/FC/SONET line cards ‌ : for high-speed Ethernet, Fibre Channel and SONET line cards.

Switches and routers ‌ : Provide a stable clock signal to ensure the synchronization and stable operation of network devices.

CPU/PCI-E applications ‌ : For processors requiring low jitter, low phase noise clocks and PCI Express applications ‌.


Consult Mingjiada Electronics immediately to get the exclusive quote for AD9575ARUZLVD. (www.hkmjd.com)


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