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AD9544BCPZ: Four-channel input, 10-channel output, dual-channel DPLL, 1 pps synchronizer and jitter eliminator

Overview

‌AD9544BCPZ is a four-channel input, 10-output clock synchronizer with dual-channel digital phase-locked loop (DPLL), 1pps synchronizer and jitter cleaner functions ‌‌, mainly used in 5G timing transmission, high-precision synchronization and phased array radar and other application scenarios ‌.

The AD9544BCPZ's 10 clock outputs are synchronized with one of up to four input reference voltage sources. A digital phase-locked loop (DPLL) reduces timing jitter associated with an external voltage reference source. With a digital control loop and hold circuit, a low jitter output signal can be continuously generated even if all reference inputs fail.

In addition, the AD9544BCPZ is available in a 48-pin LFCSP (7 mm x 7 mm) package with a temperature rating ranging from −40°C to +85°C.

Application scenario

The AD9544BCPZ is widely used in the following scenarios:

SyncE and GPS synchronization and jitter removal

Optical Transport Network (OTN), SDH, macro and small cell base stations

OTN mapping/de-mapping with jitter purification function

Small base station clock, including baseband and radio

Stratum 2, Stratum 3e and Stratum 3 hold, jitter clear and phase transient control

The JESD204B supports analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocks

Wired infrastructure

Carrier Ethernet

Its key features

The dual-channel DPLL‌ : AD9544BCPZ synchronizes physical layer clocks from 1Hz to 750 MHz, providing frequency conversion and jitter purification for a high-noise reference source ‌.

Compliant ‌ : Compliant with ITU-T G.8262 and Telcordia GR-253, the AD9544BCPZ supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824 and G.825 ‌.

Frequency monitoring and reference verification ‌ : Frequency deviation as low as 50 ppb, the AD9544BCPZ features a programmable digital loop filter bandwidth from 10^-4 Hz to 1850 Hz‌.

Reference switching function ‌ : Supports automatic and manual hold and reference switching, the AD9544BCPZ provides zero delay, no interruption or phase increment operation ‌.

Output configuration ‌ : The AD9544BCPZ has 5 pairs of clock output pins, each of which can be used as differential LVDS/HCSL/CML or 2 single-ended outputs (1 Hz to 500 MHz) ‌.

Input configuration ‌ : The AD9544BCPZ supports 2 differential or 4 single-ended input reference sources, which are interlinked to the PLL‌ by the crossover multiplexer.

In addition, the AD9544BCPZ is available in the following specifications:

Number of outputs: 10 Output

Maximum output frequency: 2415 MHz

Output level: CML, HCSL, LVCMOS, LVDS, LVPECL

Input level: CML, HCSL, LVCMOS, LVDS, LVPECL

Package/Housing: LFCSP-48

Maximum input frequency: 750 MHz

Supply voltage - Minimum: 1.71V

Power supply voltage - Max: 1.89V

Operating temperature: -40 °C to + 85°C

If you need to purchase [AD9544BCPZ], you can visit the official website www.hkmjd.com to contact Mingjiada Electronic team!