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Marvell recently announced the availability of its CPO co-packaged optical architecture for next-generation custom XPU designs in California. AI accelerators using the CPO design can scale the interconnect from tens of XPUs in a single rack to hundreds of XPUs in multiple racks.

Marvell's custom AI accelerator architecture uses high-speed SerDes, D2D interfaces and an advanced packaging architecture to combine XPU compute modules, HBM memories and other small chips with its 3D silicon photonics engine on the same substrate, enabling maximum interconnect distances between XPUs that are 100 times greater than traditional copper connections, as well as faster data transfer rates.

Marvell's CPO technology minimises electrical path lengths by integrating optics directly into a single package, which significantly reduces signal loss, enhances high-speed signal integrity and minimises latency. The design also reduces the data link's exposure to EMI interference, shortens the BOM list and improves power efficiency.

Marvell's existing 6.4Tb/s 3D silicon photonics engine integrates hundreds of components to deliver 32 200Gb/s electrical and optical I/Os, enabling 2x the bandwidth and I/O density in a single device, with up to 30% lower power consumption per bit compared to comparable devices with 100Gb/s interfaces.

Vertical expansion of AI servers requires higher signal speeds and longer connection distances to support unprecedented XPU cluster sizes,’ said Nick Kucharewski, senior vice president and general manager of Marvell's Network Switching Business Unit.

Integrating CPO devices into custom XPUs is the logical next step in the evolutionary path to scale performance with higher interconnect bandwidth and longer distances.