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12-Bit, 40 MSPS, AD9629BCPZ-40 a Monolithic, Single-Channel Analog-to-Digital Converter (ADC)

12-Bit, 40 MSPS, AD9629BCPZ-40 a Monolithic, Single-Channel Analog-to-Digital Converter (ADC)

Source:our siteTime:2024-12-12Views:

Instructions:The AD9629BCPZ-40 is a single-chip, single-channel, 12-bit, 40 MSPS analog-to-digital converter (ADC) powered by a 1.8V supply, with a built-in high-performance sample-and-hold circuit and an on-chip reference voltage source. It uses a mu…

Instructions:

The AD9629BCPZ-40 is a single-chip, single-channel, 12-bit, 40 MSPS analog-to-digital converter (ADC) powered by a 1.8V supply, with a built-in high-performance sample-and-hold circuit and an on-chip reference voltage source. It uses a multistage differential pipeline architecture with built-in output error correction logic that provides 12-bit accuracy at 80 MSPS data rates and guarantees no code loss over the entire operating temperature range.


The ADC has a variety of built-in features that allow for greater device flexibility and lower system cost, such as programmable clock alignment with data and generation of programmable digital test codes. Available digital test codes include built-in fixed codes and pseudo-random codes, as well as user-defined test codes entered through the serial port interface (SPI). A differential clock input is used to control all internal conversion cycles. An optional duty cycle stabilizer (DCS) is used to compensate for large clock duty cycle fluctuations while maintaining excellent overall ADC performance.


The digital output data format is offset binary, gray code, or binary complement. A data output clock (DCO) is used to ensure that the receiving logic has the correct latching timing.

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The AD9629 features:

1.8V analog power supply

1.8V to 3.3V output power supply

Signal to noise ratio (SNR)

71.3 dBFS (9.7MHz input)

69.0 dBFS (200 MHz input)

SFDR

95 dBc (9.7 MHz input)

83 dBc (200 MHz input)

Low power consumption

45 mW (20 MSPS)

85 mW (80 MSPS)

Differential input, 700 MHz bandwidth

On-chip reference voltage source and sampling hold circuit

2 V P-P differential analog input

DNL = ±0.16 LSB

Serial port control options

Data format: offset binary, gray code, or binary complement

1, 2, or 4 integer input clock dividers

Built-in optional digital test code generation

Energy-saving power failure mode

Data clock output with programmable clock and data alignment


Application of AD9629:

communication

Diversity radio system

Multimode digital receiver:

GSM, EDGE, WCDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

Intelligent antenna system

Battery operated instrument

Handheld oscilloscope

Portable medical imaging

ultrasonic

Radar /LIDAR

PET/SPECT imaging


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