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DP83867ISRGZR [TI] A Gigabit Ethernet PHY transceiver supporting the SGMII interface

DP83867ISRGZR [TI] A Gigabit Ethernet PHY transceiver supporting the SGMII interface

Source:our siteTime:2024-12-10Views:

The DP83867ISRGZR is a robust gigabit Ethernet PHY transceiver that supports SGMII interfaces and has an industrial-grade temperature range.Applications• Motor drives• Factory automation• Fieldbus support• Industrial Embedded Computing• Wired and…

The DP83867ISRGZR is a robust gigabit Ethernet PHY transceiver that supports SGMII interfaces and has an industrial-grade temperature range.

Applications

• Motor drives

• Factory automation

• Fieldbus support

• Industrial Embedded Computing

• Wired and wireless communications infrastructure

• Test and measurement

• Consumer electronics


Functional block diagram:

功能框图.png

Description:

The DP83867 device is a robust, low-power, fully functional physical layer transceiver that integrates the PMD subllayer to support 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols. The DP83867 is optimized to provide ESD protection exceeding the 8kV IEC 61000-4-2 standard (direct contact).


The DP83867 easily implements 10/100/1000Mbps Ethernet LAN. It is directly connected to the twisted pair media via an external transformer. This device is directly connected to the MAC layer via RGMII or embedded clock SGMII.


The DP83867 provides precise clock synchronization, including synchronizing Ethernet clock output. The device has low latency and provides IEEE 1588 frame start detection.


The DP83867 features a low-power design that consumes only 457mW at full power. Wake-on-lan can be used to reduce system power consumption.


Features

• Ultra-low latency, TX < 90ns, RX < 290ns

Time Sensitive Networking (TSN) compliant

• Low power consumption: 457mW

• More than 8000V IEC 61000-4-2 ESD protection rating

• Compliant with EN55011 Class B emission standards

• 16 programmable RGMII latency modes available on RX/TX

• Integrated MDI terminal resistor

• Programmable MAC interface termination impedance

• WoL (Wake Up on LAN) packet detection

• 25MHz or 125MHz synchronous clock output

• IEEE 1588 timestamp frame start detection

• RJ45 Mirroring mode

• Fully compliant with IEEE 802.3 10BASE-Te, 100BASE-TX and 1000BASE-T specifications

• Cable diagnosis

• RGMII and SGMII MAC interface options

• Configurable I/O voltage (3.3V, 2.5V, 1.8V)

• Fast link down mode

• JTAG support


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