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The M2GL010-FG484I is the IGLOO2 family of field-programmable gate arrays (FPGAs). Microchip's mainstream SmartFusion® 2 SoCs and IGLOO® 2 FPGA family integrate an industry-standard 4-input look-up-table (LUT)-based FPGA fabric, integrated maths blocks, multiple embedded memory blocks, and a high-performance SerDes communication interface on a single chip. and high-performance SerDes communication interfaces on a single chip. Both families are the industry's most secure and reliable FPGAs, benefiting from low-power flash technology, and these next-generation devices offer up to 150K logic elements, up to 5 MB of embedded RAM, up to 16 SerDes channels, up to 4 PCI Express Gen 2 endpoints, and an integrated hard DDR3 memory controller with error correction.

M2GL010-FG484I Parameters:

Product Category: FPGA - Field Programmable Gate Array

Series: M2GL010

Number of Logic Elements: 12084 LE

Embedded memory: 0 bit

Number of inputs/outputs: 233 I/Os

Supply voltage - min: 1.2 V

Supply voltage - max: 1.2 V

Minimum operating temperature: - 40 C

Maximum operating temperature: + 100 C

Package / Case: PBGA-484

Operating supply voltage: 1.2 V

Architecture Features

High performance memory subsystem:

64 KB embedded SRAM (eSRAM)

Up to 512 KB embedded non-volatile memory (eNVM)

One SPI/COMM_BLK

DDR bridge (2 ports) with 64-bit AXI interface

Non-blocking multi-layer AHB bus matrix for multi-master solutions supporting 4 masters and 8 slaves

Two AHB/APB interfaces to the FPGA fabric (master/slave support)

Two DMA controllers for data transaction load reduction

8-channel peripheral DMA (PDMA) for data transfers between soft peripherals and embedded eSRAM in the fabric, with support for memory-to-memory transfers

eSRAM and external DDR memory for efficient data transfers between embedded real-time memories

SERDES:

Up to 16 channels of up to 5 Gbps

Dual-channel shared reference clock with single-channel rate granularity

Programmable Tx and Rx PLL for each channel

Transmitter characteristics: programmable pre-emphasis/post-emphasis, programmable impedance, programmable amplitude

Receiver features: programmable termination, programmable linear equalisation

Built-in system debugging functions: PRBS gen/chk, constant mode, loopback

Maths module:

Power-optimised, high-performance multiplication operations

Supports 18 × 18 signed multiplication (native)

Supports 17 × 17 unsigned multiplication

Supports dot product: multiplier calculation (A[8:0] × B[17:9] + A[17:9] × B[8:0]) × 29; independent third input C, 44-bit data width, using registers

Safety features

Time-tested security:

Protection against overmanufacturing and cloning

Secure boot of FPGA and processor

Outstanding reliability: SEU-immune zero-failure flash FPGA configuration

Reliable safety-critical and mission-critical systems

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