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Service Telephone:86-755-83294757
Trade Name:QCA9880-BR4A-R
Brand:QUALCOMM
Particular Year:23+
Package:BGA
Delivery Date:New and Original
Stock: 1000pcs
The QCA9880-BR4A-R s a highly integrated wireless local area network (WLAN) system-on-chip (SoC) for 5 GHz 802.11ac or 2.4/5 GHz 802.11n WLAN applications. The QCA9880 integrates an on-board CPU for low-level setup of WLAN physical layer (PHY) and RF to offload the host processor for other tasks. It enables high-performance 3x3 MIMO with three spatial streams for wireless applications demanding the highest robust link quality and maximum throughput and range. The QCA9880 integrates a multi-protocol MAC, PHY, analog-to-digital/digital-to-analog converters (ADC/DAC), 3x3 MIMO radio transceivers, and PCI Express interface in an all-CMOS device for low power consumption and small form-factor applications.
The QCA9880-BR4A-R implements half-duplex OFDM, CCK, and DSSS PHY, supporting 1.3 GBps for 802.11ac 80 MHz channel operation. It supports 802.11n up to 216.7 Mbps for 20 MHz and 450 Mbps for 40 MHz channel operations, and IEEE 802.11a/b/g data rates. Additional features include Maximal Likelihood (ML) decoding, Low-Density Parity Check (LDPC), Maximal Ratio Combining (MRC), Space Time Block Code (STBC), and On-Chip One-Time Programmable (OTP) memory to eliminate the need for an external flash and to further reduce the external component count and BOM cost. The QCA9880 supports 802.11 wireless MAC protocol, 802.11i security, Rx/Tx filtering, error recovery, and 802.11e quality of service (QoS).
Features
WLAN CPU supports low-level setup of PHY and RF to offload the host processor for other tasks
Dynamic frequency selection (DFS) in required 5-GHz bands when used as an AP
3x3 MIMO technology improves effective throughput and range over existing 802.11a/b/g products
Supports spatial multiplexing, cyclic-delay diversity (CDD), low-density parity check (LDPC), maximal ratio combining (MRC), Space Time Block Code (STBC)
Smart antenna diversity
Single-ended RF ports with integrated matching simplify board design and layout
Integrated 1.2 V switching regulator
Data rates of up to 1.3 GBps in 802.11ac 80 MHz channels
Data rates of up to 216.7 Mbps for 20 MHz channels and 450 Mbps for 40 MHz channels using reduced (short) guard interval in 802.11n mode
Supports 20/40 MHz at 2.4 GHz
Supports 20/40/80 MHz at 5 GHz
On-Chip One-Time Programmable (OTP) memory
Support for IEEE 802.11d, e, h, i, k, r, v time stamp, and w standards
WEP, TKIP, AES, and WAPI hardware encryption
PCI Express 1.1 interface
20 and 40 MHz channelization
Frame aggregation, block ACK
802.11e-compatible bursting
108-pin, 12 mm x 12 mm LPCC package
Model
Brand
Package
Quantity
Describe
Microchip
TFBGA-325
2000
SmartFusion®2 SoC FPGA based on 166MHz Arm® Cortex®-M3 CPU
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