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Service Telephone:86-755-83294757
Trade Name:LPC1837JBD144E
Data Manual:LPC1837JBD144E.pdf
Brand:NXP
Particular Year:23+
Package:LQFP144
Delivery Date:New and Original
Stock: 2000pcs
The LPC1837JBD144E is an ARM Cortex-M3 based microcontroller for embedded applications.The ARM Cortex-M3 is a new generation of cores that offers system enhancements such as low power consumption, enhanced debugging features and provides high-level block integration support.
The LPC1837JBD144E CPU operates at up to 180 MHz. the ARM Cortex-M3 CPU features a 3-stage pipeline and Harvard architecture with separate local instruction and data buses, as well as a third bus for system peripherals. the ARM Cortex-M3 CPU also includes an internal prefetch unit to support branch speculation. the LPC1837JBD144E CPU also includes an internal prefetch unit to support branch speculation. the LPC1837JBD144E CPU also includes an internal prefetch unit to support branch speculation.
The LPC1837JBD144E includes up to 1 MB of Flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, a four-channel SPI flash interface (SPIFI), a state-configurable timer (SCT) subsystem, two Hi-Speed USB controllers, Ethernet, an LCD, an external memory controller, and multiple digital and analogue peripherals.
Features
Processor Core
ARM Cortex-M3 processor with CPU frequency up to 180 MHz
ARM Cortex-M3 inbuilt memory protection unit (MPU) supporting 8 sectors
ARM Cortex-M3 built-in nestable vector interrupt controller (NVIC)
Non-maskable interrupt (NMI) inputs
JTAG and serial debug (SWD), serial trace, 8 breakpoints, and 4 watchpoints
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support
System beat timer
On-chip memory
Up to 1 MB of on-chip dual-block flash memory with flash accelerator
16 kB on-chip EEPROM data memory
136 kB SRAM for code and data
Multiple SRAM modules with independent bus access support
64 kB ROM containing boot code and on-chip software drivers
64-bit general-purpose one-time programmable (OTP) memory
Clock generation unit
Crystal oscillator operating from 1 MHz to 25 MHz
12 MHz internal RC oscillator calibrated to 2% accuracy (1% at Tamb = 0 °C to 85 °C) over full temperature and voltage range
Ultra-low power RTC crystal oscillator
Three on-chip PLLs allow the CPU to run at maximum CPU rate without the need for a high frequency crystal. The second PLL can be used for high-speed USB and the third PLL can be used as an audio PLL.
Clock outputs
Configurable digital peripherals
State Configurable Timer (SCT) subsystem on the AHB
Global Multiple Input Array (GIMA) allows cross connecting multiple inputs and outputs of event driven peripherals such as timers, SCTs and ADC0/1s.
Serial Interface
Four-channel SPI flash interface (SPIFI) with 1-, 2-, or 4-bit data rates up to 52 MB per second
10/100T Ethernet MAC supporting RMII and MII interfaces and DMA for high throughput at low CPU loads IEEE 1588 timestamp/advanced timestamp support (IEEE 1588-2008 v2)
One high-speed USB 2.0 host/device/OTG interface with DMA support and on-chip high-speed PHY (USB0)
One Hi-Speed USB 2.0 host/device interface with DMA support with on-chip Hi-Speed PHY and external Hi-Speed PHY ULPI interface (USB1)
USB interface electronic test software included in the ROM USB stack
Four DMA-enabled 550 UARTs: one UART with full modem interface, one UART with IrDA interface, three USARTs with UART synchronisation mode support, and one ISO7816-compliant smart card interface
Up to two C_CAN 2.0B controllers with one channel each. The use of C_CAN controllers excludes the operation of all other peripherals connected to the same bus bridge
Two SSP controllers with FIFO and multi-protocol functionality. Both SSPs support DMA
An ultra-fast I²C bus interface with monitor mode and open-drain I/O pins fully compliant with the I²C bus specification. Supports data rates up to 1 Mbit/s
One standard I²C bus interface with monitor mode and standard I/O pins
Two I²S interfaces, one with DMA support, one with 1 input and 1 output
Digital peripherals
External memory controller (EMC) with support for external SRAM, ROM, NOR Flash and SDRAM devices
LCD controller with DMA and one programmable display resolution up to 1024H × 768V Supports monochrome and colour STN panels and TFT colour panels; supports 1/2/4/8 bpp Colour Look-Up Tables (CLUT) and 16/24-bit direct pixel mapping
SD/MMC card interface
Eight-channel general-purpose DMA controller accesses all memories on the AHB bus and all DMA-capable AHB slaves
Up to 164 general purpose input/output (GPIO) pins with configurable pull-up/pull-down resistors
GPIO registers are located on the AHB for quick access; GPIO ports support DMA
Up to eight GPIO pins can be used as edge- and level-triggered interrupt sources.
Two GPIO group interrupt modules enable programmable format interrupts based on the input state of a group of GP input and output pins.
Four general-purpose timers/counters with capture and match functions
One motor control PWM for three-phase motor control
One Quadrature Encoder Interface (QEI)
Repeat Interrupt Timer (RI Timer)
Windowed watchdog timer
Ultra-low power real-time clock (RTC) on a separate power domain with 256-byte battery-powered backup registers
Event Logger with three inputs for event recognition and event timing; can be battery powered
Alarm timer; battery-powered
Analogue peripherals
One 10-bit DAC with DMA support and data conversion rates up to 400 kSamples/s
Two 10-bit ADCs with DMA support and data conversion rates up to 400 kSamples/s. Up to eight analogue channels in total. Each analogue input is connected to both ADCs
Unique ID for each device
Power supply
3.3 V (2.2 V to 3.6 V) single supply with on-chip regulator for core power and RTC power domains
RTC power domain can be powered separately by a 3 V battery
Four low-power modes: sleep mode, deep sleep mode, power-down mode and deep power-down mode
Processor wakes up from sleep mode via wake-up interrupts from different peripherals.
Wake-up from deep sleep mode, power-down mode and deep power-down mode via external interrupts and interrupts generated by the battery-powered blocks of the RTC power domains
Power-down detection with four independent thresholds for triggering an interrupt and forcing a reset
Power-on reset (POR)
LQFP144 package
Target Applications
Industrial
Consumer electronics
Large appliances
RFID card readers
E-Metering
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