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The LPC4337JBD144E is an Arm Cortex-M4 microcontroller for embedded applications that includes an Arm Cortex-M0 co-processor, up to 1 MB of Flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, a four-channel SPI Flash interface (SPIFI), advanced configurable peripherals such as a state configurable timer (SCT) and serial general-purpose I/O (SGPIO) interface, two high-speed USB controllers, Ethernet, LCD, an external storage controller, and multiple digital The LPC4337JBD144E's CPU operates at up to 204 MHz.

The Arm Cortex-M4 is a next-generation 32-bit core that offers system-enhancing features such as low power consumption, enhanced debugging features, and high-level block integration support.The Arm Cortex-M4 CPU contains a 3-stage pipeline with a Harvard architecture with separate local instruction and data buses, a third bus for peripherals, and an internal pre-fetch unit that includes support for speculative branching. Internal prefetch unitThe Arm Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. The core integrates a hardware floating-point unit.

The Arm Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core that is up-code and tool-compatible with the Cortex-M4 core.Designed to be used as a replacement for existing 8/16-bit microcontrollers, the Cortex-M0 coprocessor delivers excellent performance up to 204 MHz, with a simple instruction set and a shorter code length.

Features

Cortex-M4 Processor Core

Arm Cortex-M4 processor operating at up to 204 MHz

Arm Cortex-M4 built-in memory protection unit (MPU) supporting 8 sectors

Arm Cortex-M4 built-in nestable vector interrupt controller (NVIC)

Hardware floating-point unit

Non-maskable interrupt (NMI) inputs

JTAG and serial debug (SWD), serial trace, eight breakpoints, and four watchpoints

Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support

System beat timer

Cortex-M0 processor core

Arm Cortex-M0 coprocessor loads Arm Cortex-M4 main application processor

Operating frequency up to 204 MHz

JTAG

Built-in NVIC

On-chip memory

Up to 1 MB of on-chip dual-block Flash with Flash accelerator

16 kB on-chip EEPROM data memory

136 kB SRAM for code and data

Multiple SRAM modules supporting independent bus access. Two SRAM modules can be individually powered down

64 kB ROM containing boot code and on-chip software drivers

64-bit general-purpose one-time programmable (OTP) memory

Configurable digital peripherals

Serial GPIO (SGPIO) interface

State Configurable Timer (SCT) subsystem on AHB

Global Multiple Input Array (GIMA) allows cross-connection of multiple inputs and outputs of event-driven peripherals, such as timers, SCTs, and ADC0/1s

Serial Interface

Quad SPI flash interface (SPIFI) with four channels at rates up to 52 MB per second

Supports RMII interface and MII interface, 10/100T Ethernet MAC with DMA for high throughput at low CPU loads. IEEE 1588 timestamp/advanced timestamp support (IEEE 1588-2008 v2)

A DMA-enabled, high-speed USB 2.0 host/device/OTG interface with on-chip high-speed PHYs

One DMA-enabled Hi-Speed USB 2.0 host/device interface with on-chip Hi-Speed PHY and external Hi-Speed PHY ULPI interface

USB interface electronic test software included in the ROM USB stack

One 550 UART with DMA support and full modem interface

Three 550 USARTs with DMA and Synchronous Mode support have a smart card interface that conforms to the ISO7816 standard specification. One USART with IrDA interface

Up to two C_CAN 2.0B controllers with one channel each. The use of C_CAN controllers excludes the operation of all other peripherals connected to the same bus bridge

Two SSP controllers with FIFO and multi-protocol functionality. Both SSPs support DMA

One SPI controller

An ultra-fast I²C bus interface with monitor mode and open-drain I/O pins fully compliant with the I²C bus specification. Supports data rates up to 1 Mbit/s

One standard I²C bus interface with monitor mode and standard I/O pins

Two I²S interfaces, one with DMA support, one with 1 input and 1 output

Digital peripherals

External memory controller (EMC) with support for external SRAM, ROM, NOR Flash and SDRAM devices

LCD controller with DMA support and one with programmable display resolution up to 1024H × 768V Supports monochrome and colour STN panels and TFT colour panels; supports 1/2/4/8 bpp colour look-up tables (CLUT) and 16/24-bit direct pixel mapping. LPC4357/53 devices only

Secure Digital Input/Output (SD/MMC) card interface

Eight-channel general-purpose DMA controller accesses all memories on the AHB bus and all DMA-capable AHB slaves

Up to 164 general-purpose input/output (GPIO) pins with configurable pull-up/pull-down resistors

GPIO registers are located on the AHB for quick access; GPIO ports support DMA

Up to eight GPIO pins can be used as edge- and level-triggered interrupt sources.

Two GPIO group interrupt modules enable programmable format interrupts based on the input state of a group of GP input and output pins.

Four general-purpose timers/counters with capture and match functions

One pulse width modulator (PWM) for motor control, supporting three-phase motor control

1 Quadrature Encoder Interface (QEI)

Repeat Interrupt Timer (RI Timer)

Windowed Watchdog Timer (WWDT)

Ultra-low power real-time clock (RTC) on a separate power domain with 256-byte battery-powered backup registers

Alarm timer; can be battery powered

Analogue Peripherals

One 10-bit DAC with DMA support and data conversion rates up to 400 kSamples/s

Two 10-bit ADCs with DMA support and data conversion rates up to 400 kSamples/s, each with up to eight input channels

Unique ID for each device

Clock generation unit

Crystal oscillator operating from 1 MHz to 25 MHz

12 MHz internal RC oscillator calibrated to 2% accuracy (1% at Tamb = 0 °C to 85 °C) over full temperature and voltage range

Ultra-low power real-time clock (RTC) crystal oscillator

Three on-chip PLLs allow the CPU to run at maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used for high-speed USB and the third PLL can be used as an audio PLL.

Clock Outputs

Power Supply

3.3 V (2.2 V to 3.6 V) single supply with on-chip DC-DC converter for core power and RTC power domains

RTC power domain can be powered by a separate 3 V battery

Four low-power modes: sleep mode, deep sleep mode, power-down mode and deep power-down mode

Processor wakes up from sleep mode via wake-up interrupts from different peripherals.

Wake-up from deep sleep mode, power-down mode and deep power-down mode via external interrupts and interrupts generated by the battery-powered blocks of the RTC power domains

Power-down detection with four independent thresholds for triggering an interrupt and forcing a reset

Power-on reset (POR)

LQFP144 package

Target Applications

Motor control

Power management

Large appliances

RFID card readers

Embedded audio applications

Industrial Automation

E-Metering

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