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TSMC Based 20 nm Process Technology-10CX150YF780E6G Intel ® Cyclone 10 GX FPGA

TSMC Based 20 nm Process Technology-10CX150YF780E6G Intel ® Cyclone 10 GX FPGA

Source:our siteTime:2024-11-02Views:

Product Description:The 10CX150YF780E6G is an Intel Cyclone 10 GX FPGA built on TSMCs 20nm process technology that can be programmed through the advanced Quartus design environment and delivers twice the performance of the previous generation Cyclone …

Product Description:

The 10CX150YF780E6G is an Intel® Cyclone 10 GX FPGA built on TSMC's 20nm process technology that can be programmed through the advanced Quartus® design environment and delivers twice the performance of the previous generation Cyclone V FPGA. It also supports 12.5 Gbps chip-to-chip transceiver I/O and 6.6 Gbps backplane.


The adaptive logic module architecture is the same as the previous generation of FPgas, which efficiently implements logic functions, simplifies intellectual property (IP) kernel conversion between generations of devices, and improves timing convergence in devices.


The Intel® Cyclone 10 GX FPGA offers a comprehensive set of advanced energy saving features with power-optimized MultiTrack routing and core architecture to reduce power consumption.


Features:

Enhanced core architecture

20 nm process technology based on TSMC

Twice the performance of the previous generation of low-cost FPGas

High bandwidth integrated transceiver

Short-range speeds up to 12.5 Gbps

Backplane speeds up to 6.6 Gbps

The hard PCIe IP module supports GEN2x4 applications

Improved logic integration and hard IP blocks

8 Enter the Adaptive Logic Module (ALM).

Up to 11.74 megabits (Mb) of embedded memory

Variable precision digital Signal Processing (DSP) block

Fractional synthesis phase locked loop (PLL)

Hard storage controller and PHY up to 1,866 Mbps

Advanced energy saving

Comprehensive advanced energy saving features

Optimized power multitrack routing and core architecture

High performance FPGA architecture

Enhanced 8 input ALM with 4 registers

The improved multi-track routing architecture reduces congestion and reduces compilation time

Layered core clock architecture

Internal memory block

M20K to 20 Kb memory module with hard error correction code (ECC), cascading

Memory Logical Array Block (MLAB), 640 bit memory, can be cascaded


Target application:

Automotive infotainment system

Intelligent vision camera

Industrial robot

Machine vision

Industrial programmable logic controller

The Pro-AV system


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