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Launched for 614 Mbps to 3.125 Gbps transceiver application - 5CSEBA5U23C7N FPGA

Launched for 614 Mbps to 3.125 Gbps transceiver application - 5CSEBA5U23C7N FPGA

Source:our siteTime:2024-10-19Views:

Description:5CSEBA5U23C7N is a Cyclone V SE SoC FPGA built on TSMCs 28nm low power (28LP) process technology. It offers an 8-input Adaptive logic module (ALM) and precision adjustable digital signal processing (DSP) module that can support up to 13.59…

Description:

5CSEBA5U23C7N is a Cyclone® V SE SoC FPGA built on TSMC's 28nm low power (28LP) process technology. It offers an 8-input Adaptive logic module (ALM) and precision adjustable digital signal processing (DSP) module that can support up to 13.59 megabits (Mb) of embedded memory.


The family tightly integrates a dual-core ARM® Cortex-A9 MPCore processor, hardcore IP and FPGA in a single Cyclone® system-on-chip (SoC). It supports more than 128 Gbps of peak bandwidth and integrates data consistency between processor and FPGA architectures.


Main function

Embedded memory block

M10K: 10 kilobits (Kb) of memory block with soft error correction code (ECC).

Memory Logical Array Block (MLAB) : 640-bit distributed LUTRAM, up to 25% of ALM can be used as MLAB memory.

Universal I/O

Low Voltage Differential Signal (LVDS) receiver of 875 megabits per second (Mbps) and LVDS transmitter of 840 Mbps.

400 MHz/800 Mbps external memory interface.

Terminal on chip (OCT).

Support 3.3V voltage, drive strength up to 16 mA.

External memory interface

On Cyclone® V SoC devices, additional hardcore memory controllers in the HPS support DDR3, DDR2 and LPDDR2 SDRAM devices.

Hard Processor System (HPS)

The HPS consists of a dual-core Arm* Cortex* -A9 MPCore* processor, a rich set of peripherals, and a shared multi-port SDRAM memory controller.


Basic parameters:

Product: 5CSEBA5U23C7N

Specification code: SR50G

Type: Cyclone® V SE SoC FPGA

Logical element (LE) : 85000

Adaptive logic module (ALM) : 32075

Adaptive Logic module (ALM) register: 128300

Structure and I/O phase-locked loop (PLL) : 6

Maximum embedded memory: 4.45Mb

Digital Signal Processing (DSP) block: 87

Digital Signal Processing (DSP) format: Variable Precision

Hard processor system (HPS) : Single Arm* Cortex*-A9 or Dual-core Arm* Cortex*-A9

Hard memory controller: Yes

External Memory interface (EMIF) : DDR2, DDR3, LPDDR2

Number of I/ OS: 288

Package: UBGA-672


Applications:

• Energy efficiency of next generation drives

• IP CCTV monitoring

• High Definition (HD) IP camera


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