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Intel Introduces More Details on Granite Rapids-D Xeon 6 SoC, Plans Launch in H2 2025
August 27 news, Intel this month 25 ~ 27 in the United States held at Stanford University Hot Chips 2024 (HC36) academic conference introduced more about the Aspire 6 SoC (codename Granite Rapids-D) more details.Intel reconfirmed its statement at MWC …
August 27 news, Intel this month 25 ~ 27 in the United States held at Stanford University Hot Chips 2024 (HC36) academic conference introduced more about the Aspire 6 SoC (codename Granite Rapids-D) more details.
Intel reconfirmed its statement at MWC 2024 that the Xeon 6 SoCs for edge and telecoms will be available next year.
The Xeon 6 SoC ‘Granite Rapids-D’ combines an Intel 3 process-based Xeon 6 compute die with an Intel 4 edge-optimised I/O die, delivering significant improvements in performance, power efficiency and transistor density.
The SoC is available in a BGA-compatible package with two sub-families of 4-channel memory (expected to correspond to a single compute voxel) and 8-channel memory (expected to correspond to a dual compute voxel), as well as support for MCR DIMM high-speed memory.
Granite Rapids-D provides up to 32 PCIe 5.0 lanes, up to 16 PCIe 4.0 lanes, up to 16 CXL 2.0 lanes, and can be configured with dual 100Gb Ethernet ports.
The Xeon 6 SoC also features built-in accelerators such as Media Accelerator, QAT, DLB, vRAN Boost, DSA, and support for edge-oriented enhancements including extended operating temperature range and industrial-grade reliability.
Time:2024-11-18
Time:2024-11-18
Time:2024-11-18
Time:2024-11-18
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