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Recently, NEO Semiconductor announced the development of its 3D X-AI chip technology, which is designed to replace current DRAM chips in High Bandwidth Memory (HBM) and solve the data bus problem by implementing AI processing in 3D DRAM.

Typically, current AI chip architectures store data in high-bandwidth memory and transfer it to the GPU to perform AI algorithms (mathematical calculations) via a data bus. This architecture is inefficient and the data bus leads to long delays and high power consumption.

3D X-AI, on the other hand, uses memory cells to simulate synapses in a neural network. It supports data storage and AI operations in the same chip. The data stored in the memory cell is used directly to generate the output of the neural network without any mathematical computation, resulting in greatly improved AI performance and significant energy savings.

The 3D X-AI chip is a 3D DRAM with AI processing power in the same chip which has a neuron circuit layer on the bottom and 300 layers of storage units on the top with a capacity of 128 GB.This innovative chip can increase the performance of AI chips by 100 times and reduce power consumption by 99 per cent. With 8x higher density, it is ideally suited for storing large language models (LLMs) for generative AI applications such as Chat GPT, Gemini and CoPilot.

NEO Semiconductor describes that AI chips with NEO's 3D X-AI technology enable, 100X performance acceleration: contains 8,000 neuron circuits to perform A1 processing in 3D memory; 99% power reduction: minimises the need to transfer data to the GPU for computation, thus reducing power and heat generated by the data bus; 8X memory density: contains 300 memory layers, allowing for the storage of larger AI models. NEO estimates that each chip can support up to 10 TB/s of AI processing throughput. Using 12 3D X- AI chips stacked in an HBM package can achieve 120 TB/s processing throughput with 100X performance improvement.

3D DRAM here is also one of NEO Semiconductor's R&D directions. Unlike traditional DRAM with horizontally placed storage units, 3D DRAM vertically stacked storage units greatly increases storage capacity per unit area and improves efficiency, making it a key development direction for next-generation DRAM.

Dynamic Random Access Memory (DRAM) is used to support processors, making the use of DRAM in electronic devices more common, NEO said. However, processor speeds are growing faster than multiple generations of memory, creating a ‘performance gap’ that widens every year. Power-sensitive environments such as cloud data centres are increasingly relying on higher-powered processors to meet performance requirements, but this reduces the amount of power available for memory.

The adoption of X-DRAM architectures can reduce power consumption, lower latency, and increase throughput to overcome these and other challenges encountered with traditional DRAM. This provides higher performance for commercial systems (e.g., servers), longer battery life for mobile devices (e.g., smartphones), more functionality for edge computing devices (e.g., routers), and new deployment options for IoT objects (e.g., gateways).

3D X-DRAM's cell array structure is similar to 3D NAND Flash with FBC (capacitorless floating cell) technology, which allows a vertical structure to be formed by adding layers of masks, resulting in high yields, low costs, and significant density gains.NEO says 3D X-DRAM technology can produce a 128Gbit DRAM chip with 230 layers, which is eight times the current DRAM density is eight times higher than the current density. In recent years, SK Hynix, Samsung Electronics, Micron and other memory makers have been developing 3D DRAM technology to meet the demand for high-performance, high-capacity memory in the AI wave.