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Shenzhen Mingjiada Electronics Co., Ltd. original spot supply STM32H7B0ZBT6 microcontroller based on high-performance Arm ® Cortex ® - M7 32-bit RISC core, operating frequency up to 400MHz.

Product Features

Includes ST's latest patented technologies

Kernel

32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data cache and 16 Kbytes of instruction cache, allowing single access to a single cache line from 128-bit embedded Flash; up to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz ( Dhrystone 2.1), and DSP instruction

Memory

128 Kbyte Flash plus 1 Kbyte OTP

~1.4 Mbytes RAM: 192 Kbytes TCM RAM (including 64 Kbytes ITCM RAM + 128 Kbytes DTCM RAM for time-critical routines), 1.18 Mbytes user SRAM and 4 Kbytes backup domain SRAM

2 Octo-SPI memory interfaces with on-the-fly decryption, I/O multiplexing, support for serial PSRAM/NOR, Super RAM/Flash frame formats, and operation up to 140 MHz in SRD mode and 110 MHz in DTR mode.

Flexible external memory controller with up to 32-bit data bus:

SRAM, PSRAM, NOR Flash, clocked up to 125 MHz in synchronous mode

SDRAM/LPSDR SDRAM,

8/16-bit NAND Flash

CRC calculation unit

Security

ROP, PC-ROP, Active Tampering, Secure Firmware Upgrade Support, Secure Access Mode

General purpose inputs/outputs

Up to 138 I/O ports with interrupt capability

Fast I/O frequency up to 133 MHz

Up to 164 5 V tolerant I/Os

Low power consumption

Stop: as low as 32 µA with full RAM retention

Standby: 2.8 µA (back-up SRAM off, RTC/LSE on, PDR off)

VBAT: 0.8 µA with RTC and LSE on

Clock Management

Internal oscillator 64 MHz HSI, 48 MHz RC, 4 MHz CSI, 32 kHz LSI

External Oscillator 4-50 MHz HSE, 32.768 kHz LSE

3 x PLLs (1 for system clock, 2 for core clock) with fractional mode

Reset and power management

2 independent power domains with independent clock gating to maximise power efficiency

CPU domain (CD) for Arm® Cortex® core and its peripherals, independently switchable in hold mode

mart Runtime Domain (SRD) for reset and clock control, power management and some peripherals

1.62 to 3.6 V application power and I/O

POR, PDR, PVD and BOR

Dedicated USB power supply with embedded 3.3 V internal regulator to power internal PHYs

Dedicated MMC power supply

Energy-efficient SMPS buck converter regulator to directly power VCORE or external circuitry

Embedded regulator (LDO) with configurable and scalable outputs to power digital circuits

Voltage scaling in run and stop modes

Standby regulator (~0.9 V)

Low power modes: sleep, stop and standby

VBAT battery operation mode with charging capability

CPU and domain power status monitoring pins

Interconnect Matrix

5 DMA controllers for CPU offloading

1 x high-speed general-purpose main direct memory access controller (MDMA)

2 x Dual-port DMA with FIFO and request router functions

1x Basic DMA with request router function

1x Basic DMA dedicated to DFSDM

Up to 35 communication peripherals

4x I2C FM+ interface (SMBus/PMBus)

5xUSART/5x UART (ISO7816 interface, LIN, IrDA, modem control) and 1xLPUART

6 SPIs, including 4 SPIs with multiplexed full-duplex I2S audio-grade precision via internal audio PLL or external clock, and 1 LP domain SPI/I2S (up to 125 MHz)

2 SAI (Serial Audio Interface)

SPDIFRX interface

SWPMI single-wire protocol master input/output interface

MDIO slave interface

2 x SD/SDIO/MMC interfaces (up to 133 MHz)

2 x CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)

1× USB OTG interface (1HS/FS)

HDMI-CEC

8 to 14-bit camera interface up to 80 MHz

8/16-bit Parallel Synchronous Data Input/Output Slave Interface (PSSI)

11 analogue peripherals

2 x ADCs with 16-bit maximum resolution (up to 24 channels, up to 3.6 MSPS)

1 x analogue and 1 x digital temperature sensor

1 x 12-bit single-channel DAC (SRD domain) + 1 x 12-bit dual-channel DAC

2 x ultra-low power comparators

2 x Operational amplifiers (8 MHz bandwidth)

2 x digital filters for sigma-delta modulators (DFSDM), 1 with 8 channels/8 filters, 1 with 2 channels/1 filter in the SRD domain

Graphics

LCD-TFT controller, up to XGA resolution

Chrom-ART Graphics Hardware Accelerator (DMA2D) for reduced CPU loading

Hardware JPEG codec

Chrom-GRC™ (GFXMMU)

Up to 19 timers and 2 watchdogs

2 x 32-bit timers with up to 4 IC/OC/PWM or pulse counters and quadrature (incremental) encoder inputs (up to 280 MHz)

2 x 16-bit Advanced Motor Control Timers (up to 280 MHz)

10 x 16-bit general purpose timers (up to 280 MHz)

3× 16-bit Low Power Timer (up to 280 MHz)

2× Watchdog (Standalone and Window)

1× SysTick Timer

RTC with sub-second accuracy and hardware calendar

Encryption Acceleration

AES chain mode: 128, 192 or 256 ECB, CBC, CTR, GCM, CCM

Hash (MD5, SHA-1, SHA-2), HMAC

2x OTFDEC AES-128, CTR mode for Octo-SPI memory encryption/decryption

1x 32-bit, NIST SP 800-90B compliant, true random generator

Debug Mode

SWD and JTAG Interface

4 Kbytes embedded trace buffer

96-bit unique ID

Company homepage: http://www.hkmjd.com/