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With the explosive growth of data today, various applications have also put forward more new technologies and demands on the market. On the one hand, the amount of data is getting larger and larger, and the utilization rate of artificial intelligence and machine learning is increasing, which brings memory and I/O interfaces, bandwidth, and performance requirements; Increasing, edge computing continues to grow, bringing about an increase in the importance of data security.

In addition, the bandwidth and delay of data processing and the security of data for autonomous driving and assisted driving of smart cars also place different requirements on technology depending on the level.

Especially in this era of continuous explosive growth of global data volume, not only the amount of data generated by users' existing applications is increasing rapidly, but also new application fields such as artificial intelligence/machine learning (AI/ML), etc. More data is being generated continuously. At the same time, the data center must also have a complete structure and infrastructure to support the transmission and storage of such a huge amount of data.

Focusing on the Chinese market, the overall data center market in the Chinese market is developing very rapidly, and there is a very substantial growth and improvement every year. As the total amount of data continues to explode exponentially, data centers are adopting new computing models, such as Disaggregated Computing or Composable Computing, which also require the simultaneous improvement of data transfer rates and data Transmission security.

This also further promotes the business growth of a large number of chip companies that are deeply engaged in data transmission and high-speed computing in 2021. The vice president of strategic marketing of Rambus, the world's leading silicon IP and chip provider, said in an interview with reporters: "In 2021, Rambus will The businesses in the market segments are constantly breaking through, the company’s financial report is very dazzling, and it has maintained a very solid growth. At the same time, we also have very strong cash flow. In 2021, our operating cash flow will reach more than 200 million US dollars, which is enough to support And to ensure the company's new strategic initiatives and continuous strong R&D investment. Rambus' business is mainly developed around data center applications, and the revenue from data centers and its market segments reaches more than 75%."

As the core bus standard in data transmission and computing systems, PCIe has also evolved from the original 1.0 era to the current 6.0 era, and has become a well-deserved "5G+AIoT" data transmission standard.

Since its official creation in the early 2000s, the PCIe standard has become the industry standard for data transfer between chips in data centers and computing applications. With the rapid development of the PCIe standard, in January this year, the relevant specifications of PCIe 6.0 were officially released, marking that the industry is rapidly entering the PCIe 6.0 era, and the data transmission rate has also improved by leaps and bounds.

In the new generation of specifications, PCIe 6.0 has many technical improvements compared to the previous generation and the previous PCIe technology. For example, before PCIe 6.0, all generations of PCIe use NRZ modulation signals. In order to achieve a data transfer rate of up to 64GT/s, PCIe 6.0 adopts PAM4 modulation signal, which can achieve lower voltage margin and higher bit error rate.

Second, PCIe 6.0 uses forward error correction (FEC). FEC is essentially an algorithmic technique that ensures the integrity of all signals in a data transmission link. In addition, in order to reduce the energy consumption of the overall system, PCIe 6.0 adopts the subversive L0p mode, which is essentially through dynamic channel allocation, allowing each channel to be closed or opened to achieve systemic energy saving.

On this basis, Rambus has launched a brand new PCIe 6.0 controller. Sulei, general manager of Rambus Greater China, said: "The data transfer rate can be as high as 64GT/s. At the same time, it also continues Rambus's continuous innovation in the field of PCIe technology. Our efforts and attempts have strengthened our leadership in the PCIe field. The controller also integrates an Integrity and Data Encryption (IDE) engine, which enables secure data transfer between PCIe lanes of different PCIe devices. Rambus PCIe 6.0 The controller has been specially optimized in terms of power consumption, area and delay, which can promote the construction of environmentally friendly data centers, reduce the need for thermal management, and reduce the cost of ownership. At the same time, it can be applied to PCIe endpoints, root ports, dual modes and switch port configurations. Today, we build on the successful production tapeout of over 400 PCIe controllers, extending Rambus’ leadership in licensing PCI Express IP once again.”

However, the birth of version 6.0 does not mean that there must be intergenerational competition between PCIe 4.0/5.0/6.0. In this regard, he explained: "Because even now, we are still observing the demand for Rambus IP for PCIe 3.0 products in the market. It's just that for a specific solution that uses PCIe as the main interface, there is a tradeoff between performance and cost. There is a tradeoff: Chip designers will have two choices, either make the chip have the right data transfer rate and performance at a particular cost point, or justify the chip with the latest technology. But in either case, PCIe's Good backward compatibility ensures that the PCIe 6.0 controllers now offered by Rambus can work with PCIe 3.0 devices to meet the data transfer needs of specific systems.”

It is reported that Rambus is expected to be in mass production around 2025. However, from the perspective of today's application-side industrial structure, the early usage scenarios of PCIe 6.0 will be high-performance computing applications, such as AI accelerators. These computing-intensive applications usually choose advanced nodes, especially 5nm and 3nm. . However, with the gradual maturity of PCIe 6.0 in the future, it will continue to sink into other application fields and become a cost-effective solution for more application scenarios. PCIe will also truly open the era of 6.0 scale.