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CDCDB803ERSLR is suitable for PCIe® generation 1 through 6 8-output clock buffers

CDCDB803ERSLR is suitable for PCIe® generation 1 through 6 8-output clock buffers

Source:本站Time:2024-01-17Views:

1. Device descriptionThe CDCDB803 is a DB800ZL-compliant 8-output LP-HCSL clock buffer capable of allocating reference clocks for 1st through 6th generation PCIe, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. Using the SMBus interface a…

1. Device description

The CDCDB803 is a DB800ZL-compliant 8-output LP-HCSL clock buffer capable of allocating reference clocks for 1st through 6th generation PCIe, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. Using the SMBus interface and the 8 Output enable pin, all 8 outputs can be configured and controlled individually. The CDCDB803 is a DB800ZL-derived buffer that meets or exceeds the DB800ZL system parameter specifications. It also meets or exceeds the DB2000Q parametric specifications.

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2. Features

• 8 LP-HCSL outputs with programmable integrated 85Ω (default) or 100Ω differential output terminals

• 8 Hardware output enabler (OE#) control device

• Additional phase jitter after using the 6th generation PCIE filter: 20fs RMS (Max)

• Additional phase jitter after using a 5th generation PCIE filter: 25fs RMS (Max)

• Additional phase jitter after using DB2000Q filter: 38fsRMS (Max)

• Support for common clock (CC) and individual benchmark (IR) architectures

- Compatible with spread spectrum

• Output to output skew: < 50ps

• Input-output delay: < 3ns

• Fail-safe input

• Programmable output conversion rate control

• 9 optional SMBus addresses

• 3.3V core and IO supply voltage

• Hardware-controlled low power mode (PD#)

• Current consumption: 72mA (Max)

• 6mm x 6mm 48-pin VQFN package


3. Application

• Microservers and tower servers

• Storage area Network and host bus adapter cards

• Network connected storage

• Hardware accelerator

• Rack server


CDCDB803ERSLR is suitable for PCIe® generation 1 to 6 8-output clock buffers.


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