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Acquisition TI Electronic IC CDCE6214LTWRGERQ1 Ultra Low Power Clock Generator
Shenzhen Mingjiada Electronics Co., Ltd. acquires TI Automotive IC CDCE6214LTWRGERQ1 supports PCIe Generation 1 to Generation 5, has a low-level effective output enable terminal ultra-low power clock generator, only recycling formal channel sources, s…
Shenzhen Mingjiada Electronics Co., Ltd. acquires TI Automotive IC CDCE6214LTWRGERQ1 supports PCIe® Generation 1 to Generation 5, has a low-level effective output enable terminal ultra-low power clock generator, only recycling formal channel sources, such as agents, traders, terminal factories and so on.
Description
The CDCE6214LTWRGERQ1 is a 4-channel, ultra-low-power, mid-level jitter clock generator for automotive applications that generates five independent clock outputs selectable between various driver modes. The input source can be a single-ended or differential input clock source, or a crystal. The CDCE6214Q1TM features a fractional N PLL that synthesises an uncorrelated base frequency at any input frequency.
Features
Complies with AEC-Q100 for automotive applications
Temperature class 2: -40°C to +105°C
Functional Safety
Documentation available for functional safety system designs
RMS jitter and spurious (12kHz - 20MHz, F out > 100MHz) allows the high performance, low power fractional N PLL to be configured as follows:
Integer mode:
Differential output: 350fs typical, 600fs maximum
LVCMOS output: 1.05ps typical, 1.5ps maximum
Fractional mode:
Differential output: 1.7ps typical, 2.1ps max.
LVCMOS output: 2.0ps typical, 4.0ps maximum
Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
Internal VCO: 2.335 GHz to 2.625 GHz
Typical power consumption: 65mA for 4 output channels, 23mA for single output channel.
Universal clock input, two reference inputs for redundant support
Differential AC coupling or LVCMOS: 10MHz to 200MHz
Crystal: 10MHz to 50MHz
Flexible output clock distribution
4-channel frequency divider: up to five unique output frequencies ranging from 24kHz to 328.125MHz
OUT0 - OUT4 pins have LVDS-like, LP-HCSL or LVCMOS outputs
Burr-free output divider switching and output channel synchronisation
Separate output enables via active-low GPIOs and registers
Frequency margin options
DCO mode: Frequency increment/decrement in steps of 10ppb or less
Fully integrated and configurable loop bandwidth: 100kHz to 1.6MHz
Level switchable from single or mixed supplies: 1.8V, 2.5V, 3.3V
Configurable GPIOs and flexible configuration options
I 2C-compatible interface: up to 400kHz
Integrated EEPROM with two page and external select pins; field programmable.
Supports 100Ω systems
Low electromagnetic emissions
Small size: 24-pin VQFN (4mm × 4mm)
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Time:2025-06-19
Time:2025-06-19
Time:2025-06-19
Time:2025-06-19
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