Automotive Microcontroller_SAK-TC234LP-32F200N AC_32-bit Single-chip Microcontroller

Latest Information: Company Dynamics; Industry Information

Home /Company Dynamics /

Automotive Microcontroller_SAK-TC234LP-32F200N AC_32-bit Single-chip Microcontroller

Source:our siteTime:2025-01-23Views:

Shenzhen Mingjiada Electronics Co., Ltd. supplies Infineon Automotive Microcontrollers_SAK-TC234LP-32F200N AC_32-bit single-chip microcontrollers with 200 MHz frequency and up to 2MB Flash memory in TQFP-144 package.Description of SAK-TC234LP-32F200NT…

Description of SAK-TC234LP-32F200N

The SAK-TC234LP-32F200N AC belongs to the AURIX™ TC23xL family. Its innovative multi-core architecture, based on up to three independent 32-bit TriCore CPUs, is designed to meet the highest safety standards while significantly increasing performance. 200 MHz TriCore, 3.3V single-voltage power supply, and powerful General Purpose Timer Modules (GTMs) are designed to reduce complexity, achieve best-in-class power consumption, and provide significant cost savings.

The TC23x product family has the following features:

- High-performance microcontrollers with one CPU core

- Energy-efficient scalar triple-core CPU (TC1.6E) with the following features:

- Binary code compatible with TC1.6P

- Operating frequency up to 200 MHz over the full temperature range

- Up to 184 Kbytes of data scratchpad RAM (DSPR)

- Up to 8 Kbyte instruction paddle RAM (PSPR)

- 8 Kbyte instruction cache (ICACHE)

- 4-line read buffer (DRB)

- Locked stepper shadow core for TC1.6E

- Multiple on-chip memories

- All embedded NVM and SRAM are ECC protected

- Up to 2 Mbyte of programme flash memory (PFLASH)

- Up to 128 Kbyte of Data Flash (DFLASH) available for EEPROM emulation

- 32 Kbyte memory (LMU)

- 512 Kbyte Memory (EMEM)

- Boot Flash Memory (BROM)

- 16-channel DMA controller for secure data transfer

- Advanced interrupt system (ECC protection)

- High-performance on-chip bus architecture

- 64-bit crossbar interconnect (SRI) for fast parallel accesses between bus master, CPU and memory

- 32-bit System Peripheral Bus (SPB) for on-chip peripherals and function units

- A bus bridge (SFI bridge)

- Optional Hardware Security Module (HSM) available on some models (see below)

- Security Management Unit (SMU) handles security monitoring alarms

- Memory Test Unit (MTU) with ECC, memory initialisation and MBIST functions

- Hardware I/O monitor (IOM) for checking digital I/Os

- Multi-function on-chip peripheral unit

- Two asynchronous/synchronous serial channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud

- Four queued SPI interface channels (QSPI) with master and slave functions up to 50 Mbit/s

- Two MultiCAN+ modules with 3CAN nodes each and 128 freely assignable message objects for efficient data processing via FIFO buffers.

- 4 Single Side Bit Transmission (SENT) channels for connecting sensors

- One FlexRayTM module with 2 channels (E-Ray) for version V2.1

- A General Timer Module (GTM) providing a powerful set of digital signal filters and timer functions for autonomous and complex input/output management.

- A Capture/Compare 6 module (two cores CCU60 and CCU61)

- One General Purpose 12 Timer Unit (GPT120)

- IEEE802.3 Ethernet MAC (ETH) with RMII and MII interfaces

- Multi-function successive approximation ADC (VADC)

- Cluster of 4 independent ADC cores

- Input voltage range of 0 V to 5.5 V (ADC supply)

- Digitally programmable I/O ports

- On-chip debug support OCDS Level 1 (CPU, DMA, on-chip bus)

- 4-wire/5-wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface

- Power management system and on-chip regulator

- Clock generation unit with system PLL and Flexray PLL

- Embedded regulators