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Renesas Electronics 72V255LA10TFG CMOS First In First Out Memory

Renesas Electronics 72V255LA10TFG CMOS First In First Out Memory

Source:our siteTime:2023-05-10Views:

Shenzhen Mingjiada Electronics Co., Ltd. introduces the Renesas 72V255LA10TFG CMOS FIFO memory, a functionally compatible version of the IDT72255 designed to run on a 3.3V power supply with very low power consumption.Description:The 72V255LA10TFG is a…

Shenzhen Mingjiada Electronics Co., Ltd. introduces the Renesas 72V255LA10TFG CMOS FIFO memory, a functionally compatible version of the IDT72255 designed to run on a 3.3V power supply with very low power consumption.


Description:

The 72V255LA10TFG is an extremely deep, high-speed CMOS first-in-first-out (FIFO) memory with clocked read and write control. These FIFOs offer a number of improvements over previous super-synchronous FIFOs, including the following:

- The frequency limitation of one clock input relative to the other has been removed. The frequency select pin (FS) has been removed so that it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, will operate at the higher frequency.

- The time required for the re-transmission operation is now fixed and shorter.

- The data delay period for the first word is now fixed and short from the time the first word is written to the empty FIFO until it can be read. (The variable clock cycle count delay associated with the delay period found on previous SuperSync devices has been eliminated on this SuperSync family.


Features:

- Choose from the following memory organisation: IDT72V255LA 8192 x 18

- Pinout compatible with IDT72V275/72V285 and IDT72V295/72V2105 SuperSync FIFO

- Functionally compatible with 5V IDT72255 series

- 10ns read/write cycle time (6.5ns access time)

- Fixed, low first word data delay time

- 5V input tolerant

- Auto power-off minimises standby power consumption

- Master reset clears entire FIFO

- Partial reset clears data, but retains programmable settings

- Retransmission operation with fixed, low first-word data delay time

- Empty, full and half full flag signalling FIFO states

- Programmable almost empty and almost full flags, each of which can default to one of two pre-selected offsets

- Partial flag programming by serial or parallel means

- Choice of IDT standard timing (using the EF and FF flags) or first word passthrough timing (using the or and IR flags)


Attributes:

Storage capacity: 144K (8K x 18)  

Function: Synchronous  

Data rate: 100MHz  

Access Time: 6.5ns  

Voltage - Supply: 3 V ~ 3.6 V  

Current - Supply (max): 55mA  

Bus Direction: Unidirectional  

Expansion Type: Depth, Width  

Programmable Flag Support: Yes  

Trunking Capability: Yes  

FWFT Support: Yes  

Operating Temperature: 0°C ~ 70°C  

Mounting Type: Surface Mount  

Package/Case: 64-LQFP  

Supplier Device Package: 64-TQFP (10x10) 


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