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The B1621PM2FDGUK-U is a 16Gb 200 ball LPDDR4 3733MHz DRAM for embedded applications.

Product: B1621PM2FDGUK-U

Type: SDRAM-LPDDR4

Storage capacity: 16 Gbit

Data bus width: 64 bit

Max clock frequency: 1.6GHz

Package/housing: FBGA-200

Applications:

Smartphones and tablets

A handheld device

Laptops and slim laptops

Wearable device

CARS

Virtual Reality (VR) and Augmented Reality (AR)

Digital cameras and camcorders

Network equipment

Industrial and embedded systems

Instructions:

Kingston's discrete Low Power Double Data Rate 4 (LPDDR4) dynamic random access memory (DRAM) is designed to meet the needs of embedded applications and offers high-speed options with lower power consumption. LPDDR4 is a DRAM designed for low power consumption in mobile devices such as smartphones, tablets, and laptops. LPDDR4 operates at higher frequencies for faster data access, better multiprocessing, and less power consumption, which is critical to extending the battery life of portable devices. This memory technology combines features such as on-chip Terminal (ODT), deep power saving mode, and more efficient signal interface to reduce energy consumption without compromising performance, making it ideal for modern mobile computing platforms.

Main features:

Dual data rate architecture: two data transfers per clock cycle

• High-speed data transmission by 8-bit prefetch pipeline architecture

Bidirectional differential data strobes (DQS and /DQS) are transmitted/received with the data and are used to collect data at the receiver

• DQS is aligned with data edges for READ; Align with data center for WRITE

Differential clock input (CK_t and CK_c)

• DLL aligns DQ and DQS conversions with CK conversions

Data desensitization (DM) writes data at the rising and falling edges of the data strobe

• Support for write cycle redundant code (CRC)

• Supports programmable precodes for reading and writing

• Programmable burst length 4/8 with nibble sequential and interleave modes

• Burst length dynamic switching

• The drive length selected by MRS

• Support for dynamic on-chip termination

• Two termination states, such as RTT_PARK and RTT_NOM, which can be switched by ODT pins

• Supports asynchronous RESET pins

• Support ZQ calibration

• Support write equalization

• This product is RoHS compliant

• Internal Vref DQ level generation available

• Support TCAR (Temperature control automatic refresh) mode

• Support LP ASR (Low power automatic self-refresh) mode

• Support command address (CA) parity (command/address) mode

• Single DRAM addressing (PDA)

• Fine-grained refresh is supported

• Geardown mode (1/2 speed, 1/4 speed)

• Support for self-refresh abort

• Supports the maximum energy saving mode

• When column grouping is applied, CAS to CAS delays (tCCD_L, tCCD_S) for columns in the same or different column group access are available

• DMI pin support for data desensitization and DBIdc functionality

• Low power consumption

• Refresh each memory

• Fully compliant with JEDEC Low Power Dual Data Rate 4 (LPDDR4) specifications

• Local self-refresh (PASR)

o Storage desensitization

o Built-in temperature sensor

Built-in temperature sensor

o Self-refresh with automatic temperature compensation (ATCSR)

o Supports automatic refresh of all storage units and directional automatic refresh of each storage unit

• Dual data rate architecture; Two data transfers per clock cycle

• Differential clock input (CK_t and CK_c) bidirectional differential data strobe (DQS_tandDQS_c) in ascending and descending CK_t along the input command; Reference DQS_t for both edge data and data desensitization

• DMI pin support for data desensitization and DBIdc functionality