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In the era of the Internet of Everything, various application terminals are fragmented and diversified, creating new demands for kernel architectures, and the open-source and open-access RiSC-V architecture has been born out of this trend.

As an open-source instruction set architecture, RiSC-V is becoming the third mainstream computing architecture alongside X86 and ARM, and more and more companies around the world are entering the RiSC-V track. According to a recent study by consulting firm SHD Group, shipments of RISC-V chips are expected to exceed 1.8 billion in 2024 and 16 billion in 2030, with a compound annual growth rate of more than 40%.

This year, AIoT, which combines IoT and AI, will become mainstream, further promoting the intelligent upgrading of thousands of industries.

Espressif Systems' RiSC-V-based Wi-Fi6 chip adopted by Apple

The latest, Apple in the official Demo Go Small with Embedded Swift, based on Espressif RiSC-V architecture Wi-Fi6 SoC ESP32-C6, demonstrated the use of this build to support the Matter protocol smart devices.

January 8 this year, Espressif officially announced the new Wi-Fi6 + Bluetooth5 SoC ESP32-C61, this chip is equipped with a 32-bit single-core RiSC-V draught, the clock frequency up to 160MHz, it is built-in 320KB bias on the SRAM, 256KB ROM, support for 2.4GHz Wi-Fi6 protocols It supports 2.4GHz Wi-Fi6 protocol, is backward compatible with 802.11b/g/n, and supports 802.11ax with only 20MHz channel bandwidth operating mode, as well as 802.11b/g/n protocols with 20/40MHz bandwidth, which can help to optimise and enhance the performance of the Internet of Things (IoT).

The ESP32-C61 integrates secure boot, flash and PSRAM encryption, providing users with cost-effective and efficient security. In addition, this chip supports a wide range of standard peripherals, and furthermore, the ESP32-C61 supports the ESP-Matter-SDK, enabling customers to quickly build Matter products.