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Shenzhen Mingjiada Electronics Co., Ltd. sells original NXP general-purpose MCU LPC2458FET180 single-chip 16/32-bit microcontroller; 512 kB flash memory, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface.

Description

The LPC2458FET180 microcontroller is the industry's only ARM7™ Flash-based MCU to offer integrated LCD support. The LPC2478 and non-Flash LPC2470 each feature two ARM® high-speed buses, allowing simultaneous operation of multiple high-bandwidth peripherals including LCDs, 10/100 Ethernet, USB full-speed device/host/OTG controllers, and two CAN channels. These MCUs are well suited for a variety of applications that use LCD panels and require network or Internet connectivity.

Features

Arm7TDMI-S™ processor running at up to 72 MHz.

512 kB of on-chip Flash program memory for In-System Programming (ISP) and In-Application Programming (IAP) functionality Flash program memory located on the Arm local bus for high-performance CPU accesses

98 kB of on-chip SRAM is included:

64 kB SRAM on the Arm local bus for high-performance CPU access.

16 KB SRAM for Ethernet interface. also available as general-purpose SRAM.

16 kB SRAM for general-purpose DMA also accessible via USB.

The 2 kB SRAM data store is powered by the real-time clock (RTC) power domain.

Dual Advanced High Performance Bus (AHB) systems allow simultaneous conflict-free use of on-chip flash memory for Ethernet DMA, USB DMA, and executable programs.

EMC supports asynchronous static memory devices such as RAM, ROM, Flash, and dynamic memories such as single data rate SDRAM.

Advanced Vector Interrupt Controller (VIC) with support for up to 32 vector interrupts.

General Purpose DMA (GPDMA) controller on the AHB for SSP, I²S, SD/MM interfaces, and memory-to-memory transfers.

Serial interface:

Ethernet MAC with MII/RMII interface and associated DMA controller. These functions are located in a separate AHB.

USB 2.0 full-speed dual-port device/host/OTG controller with on-chip PHY and associated DMA controller.

Four UARTs with fractional baud rate generators, one with modem control I/O, one with IrDA support, all with FIFOs.

Dual channel CAN controller.

SPI controller.

2 SSP controllers with FIFO and multi-protocol capability. One is a spare port for the SPI port, sharing its interruptions.SSP can be used for GPDMA controllers.

3 I²C bus interfaces (one with open-drain output, two with standard port pins).

I²S (Audio Chip Interconnect) interface for digital audio input or output. Can be used for GPDMA.

Other peripherals:

SD/MMC memory card interface.

136 general-purpose I/O pins with configurable pull-up/pull-down resistors.

Input multiplexed 10-bit ADC in 8 pins.

10-bit DAC.

4 general-purpose timer/counters with 8 capture inputs and 10 match outputs. Each timer block has an external count input.

2 PWM/Timer blocks supporting 3-phase motor control Each PWM has an external count input.

RTC with separate power domain whose clock source can be an RTC oscillator or APB clock.

The 2 kB SRAM is powered by the RTC power pin, allowing data storage even when the rest of the chip is powered down.

Watchdog Timer (WDT) The WDT can be clocked by the internal RC oscillator, RTC oscillator, or APB clock.

Standard Arm test/debug interface compatible with existing tools.

Simulation trace module supports real-time tracing.

3.3 V single supply (3.0 V to 3.6 V).

Four low-power modes: idle mode, sleep mode, power-down mode, and deep power-down mode.

Four external interrupt inputs configurable as edge/level sensitive. All GPIO pins on Port 0 and Port 2 can be used as edge-sensitive interrupt sources.

The processor wakes up from power-down mode via any interrupt that can operate in power-down mode (including external interrupts, RTC interrupts, USB activity, Ethernet wake-up interrupts, CAN bus activity, port 0/2 pin interrupts, etc.).

Two independent power domains allow power consumption to be fine-tuned according to the desired functionality.

For further power savings, each peripheral has its own clock divider. These frequency dividers help reduce dynamic power consumption by 20 to 30 per cent.

Power-down detection using independent thresholds for interrupts and forced resets.

On-chip power-on reset.

On-chip crystal oscillator operating from 1 MHz to 25 MHz.

4 MHz internal RC oscillator calibrated to 1 % accuracy for selective use as system clock. CAN and USB operation is not allowed when used as CPU clock.

An on-chip PLL allows the CPU to run at maximum CPU rate without the need for a high frequency crystal. Can be run from the main oscillator, internal RC oscillator or RTC oscillator.

Boundary scan for simplified board testing.

Universal pin function selection provides more possibilities for using on-chip peripheral functions.

Block Diagram

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