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Mingjiada Electronics Import and supply Memory IC S25FL128SAGMFI000 128Mb 3V 133MHz Serial NOR Flash Memory with high quality and competitive price, welcome to call us!

Device Overview

The S25FL128SAGMFI000 NOR Flash device is a 2.7V to 3.6V / 1.65V to 3.6V VIO volt non-volatile memory based on 65nm MIRRORBIT™ technology. 128-Mb S25FL128S FL-S NOR is designed on the Eclipse architecture with page-programming buffers, allowing users to program up to 128 words in a single operation. The 128-Mb S25FL128S FL-S NOR is designed with an Eclipse architecture with a page programming buffer that allows the user to program up to 128 words (256 bytes) in a single operation, making programming and erasing faster than previous-generation SPI programming or erasing algorithms. The device connects to the host system via the Serial Peripheral Interface (SPI) and supports traditional SPI unit serial inputs and outputs (Single I/O or SIO), optional two-bit (Dual I/O or DIO) and four-bit (Quad I/O or QIO) serial commands.

As part of the FL-S family, the S25FL128S FL-S NOR supports Double Data Rate (DDR) read commands for SIO, DIO, and QIO, which transfer addresses and read data on both edges of the clock. Using the FL-S device at the higher clock rates supported by the QIO or DDR-QIO commands, the command read transfer rate is comparable to or faster than traditional parallel interface asynchronous NOR flash, while significantly reducing the number of signals.The S25FL128S FL-S NOR delivers not only the high-density performance, but also the flexibility and speed required for a wide range of embedded applications.

Product Features

3.0-volt CMOS core with multi-function I/Os

Multiple input/output serial peripheral interface (SPI)

SPI clock polarity and phase modes 0 and 3

Double data rate (DDR) option

24-bit or 32-bit extended addressing options

Serial command set and footprint compatible with S25FL-A, S25FL-K and S25FL-P SPI families

Multi-I/O command set and footprint compatible with S25FL-P SPI series

Read Commands

Normal, Fast, Dual Channel, Quad, Fast DDR, Dual Channel DDR, Quad DDR

Autostart - at power-up or reset, normal or quad read commands are automatically executed at a preselected address

Common Flash Interface (CFI) data for configuration information

Programming (1.5 Mbytes/s)

256- or 512-byte page programming buffer option

Four-input page programming (QPP) for slow clock systems

Automatic ECC - internal hardware error correction code generation and unit error correction

Erase (0.5 to 0.65 Mbytes/s)

Mixed sector size option: 32 physical 4-byte sectors at the top or bottom of the address space, all remaining sectors are 64 bytes, compatible with previous generation S25FL devices

Uniform sector option - always erase 256 kilobyte blocks for software compatibility with higher density and future devices

Interested parties, please contact Mr Chen:

Tel: +86 13410018555

Email: sales@hkmjd.com

Company website: www.hkmjd.com