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New and Original MXIC MX66L2G45GXRI00 Serial NOR Flash 2Gb SPI - Quad I/O, DTR

New and Original MXIC MX66L2G45GXRI00 Serial NOR Flash 2Gb SPI - Quad I/O, DTR

Source:our siteTime:2023-05-06Views:

Mingjiada Electronics sells brand new original MXIC MX66L2G45GXRI00 2Gb bit serial NOR flash memory, factory stock, competitive price, please call and contact us if you are interested!!!Product DetailsManufacturer: MXICProduct Model: MX66L2G45GXRI00Ye…

Mingjiada Electronics sells brand new original MXIC MX66L2G45GXRI00 2Gb bit serial NOR flash memory, factory stock, competitive price, please call and contact us if you are interested!!!


Product Details

Manufacturer: MXIC

Product Model: MX66L2G45GXRI00

Year: 2126+

Description:The MX66L2G45GXRI00 has a serial peripheral interface and a software protocol that allows operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI) and a serial data output (SO). Serial access to the device is enabled by the CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 and SIO1 pins for address/virtual bit input and data output. When it is in four I/O read modes, the SI, SO, WP# and NC pins become SIO0, SIO1, SIO2 and SIO3 pins for address/virtual bit input and data output.

MX66L2G45GXRI00 MXSMIO (Serial Multi I/O) provides sequential read operation of the entire chip.


Features:

General

-Support for serial peripheral interfaces - Mode 0 and Mode 3

-Single power supply operation - 2.7 to 3.6 volts for read, erase and program operations

-Protocol support - single input/output, dual input/output and quad input/output

-Fast read in SPI mode -Supports fast clock frequencies up to 166MHz

-Support for fast read, 2READ, DREAD, 4READ, QREAD instructions

-DTR (Double Transfer Rate) mode support -Configurable number of pseudo-cycles for fast read operation

-Provides Quad Peripheral Interface (QPI)

-Equal sectors of 4K bytes each, or equal blocks of 32K bytes each, or identical blocks of 64K bytes each -Any block can be individually erased

-Programmed with:

-256 byte page buffer

-Four input/output page program (4PP) to improve program performance

-Typical 100,000 erase/programming cycles

-20 year data retention period


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