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The ZL30256LFG7 is a 3-channel, 10-input / 18-output jitter attenuator.

Instructions:

The ZL30256 is a multi-channel high-performance, arbitrary rate multiplier and jitter attenuator that simplifies board design by generating ultra-low jitter clock signals or attenuating clock signals while generating additional independent frequency families.

ZL30256LFG7 features:

Up to 3 separate DPLL channels

Excellent jitter performance of 180fs RMS in the 12kHz to 20MHz band to meet the jitter requirements of 10G/40G and 100G PHyS

Two programmable ultra-low jitter synthesizers can generate any frequency between 1Hz and 1045MHz

A programmable general-purpose synthesizer can generate any clock frequency in the range of 1Hz to 180MHz

Eight differential or 16 single-ended (CMOS) ultra-low jitter outputs as well as two general purpose CMOS outputs

Accept up to 10 LVPECL/LVDS/HCSL/LVCMOS inputs

Any input reference voltage source can be fed by clock, sync (frame pulses), clock/sync pairs, or clocks modulated by sync pulses (embedded PPS ePPS and embedded PP2S ePP2S)

Up to four programmable digital PLLS/Ncos with loop bandwidths ranging from 14Hz to 470Hz, can be synchronized to any clock rate from 1kHz to 900MHz, and synchronized to clock and sync pulses

Automatic uninterrupted reference switching and digital hold in case of reference failure, initial hold accuracy better than 1ppb (with post-hold filter)

Easy configuration and dynamic programming via SPI/I2C interface

Powered by a single crystal resonator or clock oscillator

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