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450MHz FPGA LFMXO5-25-8BBG400I MachXO3 Field Programmable Gate Array IC 400-CABGA

Product Description Of LFMXO5-25-8BBG400I

LFMXO5-25-8BBG400I provides low-skew, high fan-out clock distribution to all synchronous elements in the FPGA fabric through the Primary Clock Network.

LFMXO5-25-8BBG400I PCLK clock network is a balanced clock structure which is designed to minimize the clock skew among all the final destination of the IPs in the FPGA core that needs a clock source.

Feature Of LFMXO5-25-8BBG400I

1.4 Mb sysMEM™ Embedded Block RAM (EBR)

Programmable width

Error Correction Coding (ECC)*

First Input First Output (FIFO)

80 kbit distributed RAM

Large RAM Blocks

0.5 Mb per block

Internal bus interface support

APB control bus

AHB-Lite for data bus

AXI4-streaming

Non-Volatile Configuration – Fast, Secure, On-chip

multi-boot

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